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72T18115L6-7BBGI中文資料瑞薩數(shù)據(jù)手冊(cè)PDF規(guī)格書(shū)

72T18115L6-7BBGI
廠商型號(hào)

72T18115L6-7BBGI

功能描述

2.5 VOLT HIGH-SPEED TeraSync? FIFO 18-BIT/9-BIT CONFIGURATIONS

文件大小

492.5 Kbytes

頁(yè)面數(shù)量

57 頁(yè)

生產(chǎn)廠商 Renesas Technology Corp
企業(yè)簡(jiǎn)稱

RENESAS瑞薩

中文名稱

瑞薩科技有限公司官網(wǎng)

原廠標(biāo)識(shí)
數(shù)據(jù)手冊(cè)

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更新時(shí)間

2025-2-11 14:36:00

72T18115L6-7BBGI規(guī)格書(shū)詳情

FEATURES:

? Choose among the following memory organizations:

IDT72T1845 ? 2,048 x 18/4,096 x 9

IDT72T1855 ? 4,096 x 18/8,192 x 9

IDT72T1865 ? 8,192 x 18/16,384 x 9

IDT72T1875 ? 16,384 x 18/32,768 x 9

IDT72T1885 ? 32,768 x 18/65,536 x 9

IDT72T1895 ? 65,536 x 18/131,072 x 9

IDT72T18105 ? 131,072 x 18/262,144 x 9

IDT72T18115 ? 262,144 x 18/524,288 x 9

IDT72T18125 ? 524,288 x 18/1,048,576 x 9

? Up to 225 MHz Operation of Clocks

? User selectable HSTL/LVTTL Input and/or Output

? Read Enable & Read Clock Echo outputs aid high speed operation

? User selectable Asynchronous read and/or write port timing

? 2.5V LVTTL or 1.8V, 1.5V HSTL Port Selectable Input/Ouput voltage

? 3.3V Input tolerant

? Mark & Retransmit, resets read pointer to user marked position

? Write Chip Select (WCS) input enables/disables Write operations

? Read Chip Select (RCS) synchronous to RCLK

? Programmable Almost-Empty and Almost-Full flags, each flag can

default to one of eight preselected offsets

? Program programmable flags by either serial or parallel means

? Selectable synchronous/asynchronous timing modes for Almost-

Empty and Almost-Full flags

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14099
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RENESAS(瑞薩)/IDT
23+
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7350
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原裝
1922+
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1550
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24+
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53200
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IDT/RENESAS
22+
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24500
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2021+
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499
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23+
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6000
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RENESAS ELECTRONICS
22+
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518000
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RENESAS(瑞薩)/IDT
1921+
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3575
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6850
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