74ACT161集成電路（IC）的計(jì)數(shù)器除法器規(guī)格書PDF中文資料

74ACT161屬于集成電路（IC）的計(jì)數(shù)器除法器。由意法半導(dǎo)體集團(tuán)制造生產(chǎn)的74ACT161計(jì)數(shù)器，除法器計(jì)數(shù)器和除法器 IC 是數(shù)字邏輯器件，可對輸入發(fā)生的邏輯轉(zhuǎn)換進(jìn)行計(jì)數(shù)，然后使用多個并行輸出重新發(fā)送累加的計(jì)數(shù)，和/或生成單個輸出信號轉(zhuǎn)換，從而對應(yīng)用某些整數(shù)數(shù)量輸入信號轉(zhuǎn)換進(jìn)行響應(yīng)。除了簡單的事件計(jì)數(shù)，它們還可用于各種頻率合成應(yīng)用。

DESCRIPTION

The 74ACT161 is an advanced high-speed CMOS SYNCRONOUS PRESETTABLE COUNTER fabricated with sub-micron silicon gate and double-layer metal wiring C2MOS tecnology. It is a 4 bit binary counter with Asynchronous Clear.

The circuit have four fundamental modes of operation, in order of preference: synchronous reset, parallel load, count-up and hold. Four control inputs, (CLEAR), (LOAD), (PE) and (TE), determine the mode of operation as shown in the Truth Table. A LOW signal on CLEAR overrides counting and parallel loading and sets all outputs on LOW state. A LOW signal on LOAD overrides counting and allows information on Parallel Data inputs to be loaded into the flip-flop on the next rising edge of CLOCK. With LOAD and CLEAR HIGH, PE and TE permit counting when both are HIGH. Conversely, a LOW signal on either PE and TE inhibits counting.

The CARRY OUTPUT is HIGH when TE is HIGH and counter is in state 15.

The device is designed to interface directly High Speed CMOS systems with TTL, NMOS and CMOS output voltage levels.

All inputs and outputs are equipped with protection circuits against static discharge, giving them 2KV ESD immunity and transient excess voltage.

■ HIGH SPEED:

fMAX = 290MHz (TYP.) at VCC = 5V

■ LOW POWER DISSIPATION:

ICC = 8μA(MAX.) at TA=25°C

■ COMPATIBLE WITH TTL OUTPUTS

VIH = 2V (MIN.), VIL = 0.8V (MAX.)

■ 50? TRANSMISSION LINE DRIVING CAPABILITY

■ SYMMETRICAL OUTPUT IMPEDANCE:

|IOH| = IOL = 24mA (MIN)

■ BALANCED PROPAGATION DELAYS: tPLH ? tPHL

■ OPERATING VOLTAGE RANGE:

VCC (OPR) = 4.5V to 5.5V

■ PIN AND FUNCTION COMPATIBLE WITH 74 SERIES 161

■ IMPROVED LATCH-UP IMMUNITY