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74HCT163DB集成電路(IC)的計(jì)數(shù)器除法器規(guī)格書(shū)PDF中文資料
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廠商型號(hào) |
74HCT163DB |
參數(shù)屬性 | 74HCT163DB 封裝/外殼為16-SSOP(0.209",5.30mm 寬);包裝為管件;類(lèi)別為集成電路(IC)的計(jì)數(shù)器除法器;產(chǎn)品描述:IC SYNC 4BIT BINARY COUNT 16SSOP |
功能描述 | Presettable synchronous 4-bit binary counter; synchronous reset |
封裝外殼 | 16-SSOP(0.209",5.30mm 寬) |
文件大小 |
309.8 Kbytes |
頁(yè)面數(shù)量 |
20 頁(yè) |
生產(chǎn)廠商 | Nexperia B.V. All rights reserved |
企業(yè)簡(jiǎn)稱(chēng) |
NEXPERIA【安世】 |
中文名稱(chēng) | 安世半導(dǎo)體(中國(guó))有限公司官網(wǎng) |
原廠標(biāo)識(shí) | ![]() |
數(shù)據(jù)手冊(cè) | |
更新時(shí)間 | 2025-2-11 18:26:00 |
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1. General description
The 74HC163; 74HCT163 is a synchronous presettable binary counter with an internal look-head
carry. Synchronous operation is provided by having all flip-flops clocked simultaneously on the
positive-going edge of the clock (CP). The outputs (Q0 to Q3) of the counters may be preset to
a HIGH or LOW. A LOW at the parallel enable input (PE) disables the counting action. It causes
the data at the data inputs (D0 to D3) to be loaded into the counter on the positive-going edge of
the clock. Preset takes place regardless of the levels at count enable inputs (CEP and CET). A
LOW at the master reset input (MR) sets Q0 to Q3 LOW after the next positive-going transition
on the clock input (CP). This action occurs regardless of the levels at input pins PE, CET and
CEP. This synchronous reset feature enables the designer to modify the maximum count with
only one external NAND gate. The look-ahead carry simplifies serial cascading of the counters.
Both CEP and CET must be HIGH to count. The CET input is fed forward to enable the terminal
count output (TC). The TC output thus enabled will produce a HIGH output pulse of a duration
approximately equal to a HIGH output of Q0. This pulse can be used to enable the next cascaded
stage. Inputs include clamp diodes. This enables the use of current limiting resistors to interface
inputs to voltages in excess of VCC.
The CP to TC propagation delay and CEP to CP set-up time determine the maximum clock
frequency for the cascaded counters according to the following formula:
2. Features and benefits
? Complies with JEDEC standard no. 7A
? Input levels:
? For 74HC163: CMOS level
? For 74HCT163: TTL level
? Synchronous counting and loading
? 2 count enable inputs for n-bit cascading
? Synchronous reset
? Positive-edge triggered clock
? ESD protection:
? HBM JESD22-A114F exceeds 2 000 V
? MM JESD22-A115-A exceeds 200 V
? Multiple package options
? Specified from -40 °C to +85 °C and -40 °C to +125 °C
產(chǎn)品屬性
- 產(chǎn)品編號(hào):
74HCT163DB,118
- 制造商:
Nexperia USA Inc.
- 類(lèi)別:
集成電路(IC) > 計(jì)數(shù)器,除法器
- 系列:
74HCT
- 包裝:
管件
- 邏輯類(lèi)型:
二進(jìn)制計(jì)數(shù)器
- 方向:
上
- 復(fù)位:
同步
- 定時(shí):
同步
- 觸發(fā)器類(lèi)型:
正邊沿
- 工作溫度:
-40°C ~ 125°C
- 安裝類(lèi)型:
表面貼裝型
- 封裝/外殼:
16-SSOP(0.209",5.30mm 寬)
- 供應(yīng)商器件封裝:
16-SSOP
- 描述:
IC SYNC 4BIT BINARY COUNT 16SSOP
供應(yīng)商 | 型號(hào) | 品牌 | 批號(hào) | 封裝 | 庫(kù)存 | 備注 | 價(jià)格 |
---|---|---|---|---|---|---|---|
Nexperia(安世) |
23+ |
SO16 |
6000 |
誠(chéng)信服務(wù),絕對(duì)原裝原盤(pán) |
詢(xún)價(jià) | ||
NXP |
21+ |
16SSOP |
13880 |
公司只售原裝,支持實(shí)單 |
詢(xún)價(jià) | ||
ph |
24+ |
N/A |
6980 |
原裝現(xiàn)貨,可開(kāi)13%稅票 |
詢(xún)價(jià) | ||
Nexperia(安世) |
22+ |
SSOP-16 |
9852 |
只做原裝正品現(xiàn)貨,或訂貨假一賠十! |
詢(xún)價(jià) | ||
PHIL |
25 |
原裝正品現(xiàn)貨庫(kù)存價(jià)優(yōu) |
詢(xún)價(jià) | ||||
Nexperia(安世) |
1923+ |
SSOP-16 |
2260 |
向鴻只做原裝正品,我們沒(méi)有假貨!倉(cāng)庫(kù)庫(kù)存優(yōu)勢(shì) |
詢(xún)價(jià) | ||
HAR |
24+ |
DIP |
615 |
詢(xún)價(jià) | |||
PHI |
24+ |
TSOP-24 |
25843 |
公司原廠原裝現(xiàn)貨假一罰十!特價(jià)出售!強(qiáng)勢(shì)庫(kù)存! |
詢(xún)價(jià) | ||
Nexperia(安世) |
23+ |
SSOP16208mil |
7350 |
現(xiàn)貨供應(yīng),當(dāng)天可交貨!免費(fèi)送樣,原廠技術(shù)支持!!! |
詢(xún)價(jià) | ||
Nexperia |
22+ |
NA |
500000 |
萬(wàn)三科技,秉承原裝,購(gòu)芯無(wú)憂 |
詢(xún)價(jià) |