74LVC2G241GT集成電路（IC）的緩沖器驅動器接收器收發(fā)器規(guī)格書PDF中文資料

廠商型號	74LVC2G241GT
參數(shù)屬性	74LVC2G241GT 封裝/外殼為8-XFDFN；包裝為管件；類別為集成電路（IC）的緩沖器驅動器接收器收發(fā)器；產(chǎn)品描述：IC BUFFER NON-INVERT 5.5V 8XSON
功能描述	Dual buffer/line driver; 3-state
絲印標識	V41
封裝外殼	SOT833-1 / 8-XFDFN
文件大小	274.15 Kbytes
頁面數(shù)量	18 頁
生產(chǎn)廠商	Nexperia B.V. All rights reserved
企業(yè)簡稱	NEXPERIA【安世】
中文名稱	安世半導體(中國)有限公司官網(wǎng)
原廠標識
數(shù)據(jù)手冊	下載地址一下載地址二到原廠下載
更新時間	2025-3-29 23:00:00
人工找貨	74LVC2G241GT價格和庫存，歡迎聯(lián)系客服免費人工找貨

1. General description

The 74LVC2G241 is a dual non-inverting buffer/line driver with 3-state outputs. The 3-state outputs

are controlled by the output enable inputs 1OE and 2OE:

? A HIGH level at pin 1OE causes output 1Y to assume a high-impedance OFF-state.

? A LOW level at pin 2OE causes output 2Y to assume a high-impedance OFF-state.

Schmitt trigger action at all inputs makes the circuit highly tolerant of slower input rise and fall

times.

Inputs can be driven from either 3.3 V or 5 V devices. This feature allows the use of the

74LVC2G241 as a translator in a mixed 3.3 V and 5 V environment.

This device is fully specified for partial power-down applications using IOFF. The IOFF circuitry

disables the output, preventing a damaging backflow current through the device when it is powered

down.

2. Features and benefits

? Wide supply voltage range from 1.65 V to 5.5 V

? 5 V tolerant input/output for interfacing with 5 V logic

? High noise immunity

? Complies with JEDEC standard:

? ? JESD8-7 (1.65 V to 1.95 V)

? JESD8-5 (2.3 V to 2.7 V)

? JESD8-B/JESD36 (2.7 V to 3.6 V)

? ESD protection:

? ? HBM JESD22-A114F exceeds 2000 V

? MM JESD22-A115-A exceeds 200 V

? ±24 mA output drive (VCC = 3.0 V)

? CMOS low power consumption

? Latch-up performance exceeds 250 mA

? Direct interface with TTL levels

? Inputs accept voltages up to 5 V

? Multiple package options

? Specified from -40 °C to +85 °C and -40 °C to +125 °C