74V1G14S集成電路（IC）的門反相器規(guī)格書PDF中文資料

74V1G14S屬于集成電路（IC）的門反相器。由意法半導(dǎo)體集團制造生產(chǎn)的74V1G14S門和反相器邏輯柵極和逆變器系列中的產(chǎn)品對單個邏輯信號執(zhí)行基本邏輯運算（例如 AND、NOT、OR 等）。與觸發(fā)器不同，它們不能夠存儲信息，不會對提供給其輸入的信號立即做出響應(yīng)。雖然早就被集成電路實施形式所取代，以用于實現(xiàn)復(fù)雜功能，但分立柵極仍可在僅需要非常簡單邏輯功能的情況下使用。

DESCRIPTION

The 74V1G14 is an advanced high-speed CMOS SINGLE SCHMITT INVERTER fabricated with sub-micron silicon gate and double-layer metal wiring C2MOS technology.

The internal circuit is composed of 3 stages including buffer output, which provide high noise immunity and stable output.

Power down protection is provided on input and 0 to 7V can be accepted on input with no regard to the supply voltage. This device can be used to interface 5V to 3V. Pin configuration and function are the same as those of the 74V1G04 but the 74V1G14 has hysteresis.

This together with its schmitt trigger function allows it to be used on line receivers with slow rise/fall input signals.

The input is equipped with protection circuits against static discharge, giving it ESD immunity and transient excess voltage.

■ HIGH SPEED: tPD = 4.3ns (TYP.) at VCC = 5V

■ LOW POWER DISSIPATION: ICC = 1μA(MAX.) at TA=25°C

■ TYPICAL HYSTERESIS: Vh=1V at VCC=4.5V

■ POWER DOWN PROTECTION ON INPUT

■ SYMMETRICAL OUTPUT IMPEDANCE: |IOH| = IOL = 8mA (MIN) at VCC = 4.5V

■ BALANCED PROPAGATION DELAYS: tPLH ? tPHL

■ OPERATING VOLTAGE RANGE: VCC(OPR) = 2V to 5.5V

■ IMPROVED LATCH-UP IMMUNITY