85304-01中文資料IDT數(shù)據(jù)手冊PDF規(guī)格書

General Description

The 85304-01 is a low skew, high performance 1-to-5 Differential-to-3.3V LVPECL fanout buffer. The 85304-01 has two selectable clock inputs. The CLKx, nCLKx pairs can accept most standard differential input levels. The clock enable is internally synchronized to eliminate runt clock pulses on the outputs during asynchronous assertion/ deassertion of the clock enable pin.

Features

? Five 3.3V differential LVPECL output pairs

? Selectable differential CLKx, nCLKx input pairs

? CLKx, nCLKx input pairs can accept the following differential

levels: LVDS, LVPECL, LVHSTL, SSTL and HCSL levels

? Maximum output frequency: 650MHz

? Translates any single-ended input signal to 3.3V LVPECL levels

with resistor bias on nCLKx inputs

? Output skew: 35ps (maximum)

? Part-to-part skew: 150ps (maximum)

? Propagation delay: 2.1ns (maximum)

? Full 3.3V supply mode

? 0°C to 70°C ambient operating temperature