85408BGILFT

Marking：ICS85408BGILF；Package：TSSOP；Low Skew, 1-to-8, Differential-to-LVDS Clock

Features ?EightdifferentialLVDSoutputpairs ?Onedifferentialclockinputpair ?CLK,nCLKcanacceptthefollowingdifferentialinputlevels: LVPECL,LVDS,LVHSTL,HCSL,SSTL ?Maximumoutputfrequency:700MHz ?Translatesanydifferentialinputsignal(LVPECL,LVHSTL,SSTL, HCSL)to

85408BGILFT

Marking：ICS85408BGILF；Package：TSSOP；Low Skew, 1-to-8 , Different ial-to-LVDS Clock

85408BGILFT

Package：24-TSSOP（0.173"，4.40mm 寬）；包裝：卷帶（TR） 類別：集成電路（IC） 時鐘緩沖器，驅(qū)動器 描述：IC CLK BUFFER 1:8 700MHZ 24TSSOP

Renesas Electronics America Inc

85408BGLF

LowSkew,1-to-8,Differential-to-LVDSClock

85408BGLF

LowSkew,1-to-8,Differential-to-LVDSClock

Features ?EightdifferentialLVDSoutputpairs ?CLK/nCLKcanacceptthefollowingdifferentialinputlevels: LVPECL,LVDS,LVHSTL,HCSL,SSTL ?Maximumoutputfrequency:700MHz ?Translatesanydifferentialinputsignal(LVPECL,LVHSTL,SSTL, HCSL)toLVDSlevelswithoutexternalbiasnetw

85408BGLFT

LowSkew,1-to-8,Differential-to-LVDSClock

85408BGLFT

LowSkew,1-to-8,Differential-to-LVDSClock

Features ?EightdifferentialLVDSoutputpairs ?CLK/nCLKcanacceptthefollowingdifferentialinputlevels: LVPECL,LVDS,LVHSTL,HCSL,SSTL ?Maximumoutputfrequency:700MHz ?Translatesanydifferentialinputsignal(LVPECL,LVHSTL,SSTL, HCSL)toLVDSlevelswithoutexternalbiasnetw

85408I

LowSkew,1-to-8,Differential-to-LVDSClock

Features ?EightdifferentialLVDSoutputpairs ?Onedifferentialclockinputpair ?CLK,nCLKcanacceptthefollowingdifferentialinputlevels: LVPECL,LVDS,LVHSTL,HCSL,SSTL ?Maximumoutputfrequency:700MHz ?Translatesanydifferentialinputsignal(LVPECL,LVHSTL,SSTL, HCSL)to

85408I

LowSkew,1-to-8,Differential-to-LVDSClock

ICS85408

LOWSKEW,1-TO-8DIFFERENTIAL-TO-LVDSCLOCKDISTRIBUTIONCHIP

GENERALDESCRIPTION TheICS85408isalowskew,highperformance1-to-8Differential-to-LVDSClockDistributionChipandamemberoftheHiPerClockS?familyofHighPerformanceClockSolutionsfromICS.TheICS85408CLK,nCLKpaircanacceptmostdifferentialinputlevelsandtranslatesthemto3