874001I-02中文資料瑞薩數(shù)據(jù)手冊(cè)PDF規(guī)格書

Features

? One differential LVDS output pair

? One differential clock input

? CLK, nCLK can accept the following differential input levels:

LVPECL, LVDS, LVHSTL, HCSL, SSTL

? Input frequency range: 98MHz to 128MHz

? Output frequency range: 98MHz to 640MHz

? VCO range: 490MHz - 640MHz

? Cycle-to-cycle jitter: 15ps (maximum), 3.3V

? RMS period jitter: 3ps (maximum), 3.3V

? Two bandwidth modes allow the system designer to make jitter

attenuation/tracking skew design trade-offs

? Full 3.3V or 2.5V operating supply

? -40°C to 85°C ambient operating temperature

? Available in lead-free (RoHS 6) package

General Description

The ICS874001I-02 is a high performance Jitter Attenuator designed

for use in PCI Express? systems. In some PCI Express systems,

such as those found in desktop PCs, the PCI Express clocks are

generated from a low bandwidth, high phase noise PLL frequency

synthesizer. In these systems, a jitter attenuator may be required to

attenuate high frequency random and deterministic jitter

components from the PLL synthesizer and from the system board.

The ICS874001I-02 has two different PLL bandwidth modes: 2MHz

and 3MHz. The 2MHz mode will provide maximum jitter attenuation,

but with higher PLL tracking skew and spread spectrum modulation

from the motherboard synthesizer may be attenuated. The 3MHz

bandwidth provides the best tracking skew and will pass most

spread profiles, but the jitter attenuation will not be as good as the

lower bandwidth mode. The 874001I-02 can be set for different

modes using the F_SELx pins, as shown in Table 3C.

The ICS874001I-02 uses IDT’s 3RD Generation FemtoClock?

PLL technology to achieve the lowest possible phase noise. The

device is packaged in a small 20-pin TSSOP package, making it

ideal for use in space constrained applications such as PCI Express

add-in cards.