8T33FS6111中文資料瑞薩數(shù)據(jù)手冊PDF規(guī)格書

General Description

The 8T33FS6111 is a bipolar monolithic differential clock fanout

buffer. Designed for most demanding clock distribution systems, the

8T33FS6111 supports various applications that require distribution

of precisely aligned differential clock signals. Using SiGe:C

technology and a fully differential architecture, the device offers very

low skew outputs and superior digital signal characteristics. Target

applications for this clock driver is high performance clock distribution

in computing, networking and telecommunication systems.

The 8T33FS6111 is designed for low skew clock distribution systems

and supports clock frequencies up to 2.7GHz. The device accepts

two clock sources. The CLKA input can be driven by LVPECL

compatible signals, the CLKB input accepts HSTL or LVPECL

compatible signals. The selected input signal is distributed to 10

identical, LVPECL outputs. If VBB is connected to the CLKA input and

bypassed to GND by a 10nF capacitor, the 8T33FS6111 can be

driven by single-ended LVPECL signals utilizing the VBB bias voltage

output.

In order to meet the tight skew specification of the device, both

outputs of a differential output pair should be terminated, even if only

one output is used. In the case where not all ten outputs are used,

the output pairs on the same package side as the parts being used

on that side should be terminated.

The 8T33FS6111 can be operated from a single 3.3V or 2.5V supply

Features

? 1:10 differential clock distribution

? 28ps typical output skew

? Fully differential architecture from input to all outputs

? SiGe:C technology supports near-zero output skew

? Supports DC to 2.7GHz operation of clock or data signals

? LVPECL compatible differential clock outputs

? LVPECL/HSTL compatible differential clock inputs

? Single 3.3V or 2.5V supply

? Standard 32-Lead VFQFN package

? Standard 32-lead LQFP package

? Standard 32-lead TQFP package with EPAD

? -40°C to 85°C ambient operating temperature