8T74S208B中文資料瑞薩數(shù)據(jù)手冊PDF規(guī)格書

Description

The 8T74S208B is a high-performance differential LVDS clock divider

and fanout buffer. The device is designed for the frequency division

and signal fanout of high-frequency, low phase-noise clocks. The

8T74S208B is characterized to operate from a 2.5V power supply.

Guaranteed output-to-output and part-to-part skew characteristics

make the 8T74S208B ideal for those clock distribution applications

demanding well-defined performance and repeatability. The

integrated input termination resistors make interfacing to the

reference source easy and reduce passive component count. Each

output can be individually enabled or disabled in the high-impedance

state controlled by a I2C register. On power-up, all outputs are

enabled.

Features

? One differential input reference clock

? Differential pair can accept the following differential input

levels: LVDS, LVPECL, CML

? Integrated input termination resistors

? Eight LVDS outputs

? Selectable clock frequency division of ÷1, ÷2, ÷4 and ÷8

? Maximum input clock frequency: 1GHz

? LVCMOS interface levels for the control inputs

? Individual output enabled/ disabled by I2C interface

? Output skew: 45ps (maximum)

? Output rise/fall times: 370ps (maximum)

? Low additive phase jitter, RMS: 96fs (typical)

? Full 2.5V supply voltage

? Outputs enabled at power up

? Lead-free (RoHS 6) 32-Lead VFQFN packaging

? -40°C to 85°C ambient operating temperature