AD6650RF/IF射頻/中頻RFID的RFIC模塊規(guī)格書PDF中文資料

AD6650屬于RF/IF射頻/中頻RFID的RFIC模塊。由亞德諾半導(dǎo)體技術(shù)有限公司制造生產(chǎn)的AD6650RF 其它 IC 和模塊RF 其它 IC 和模塊產(chǎn)品系列包含各種獨(dú)特、專門或特定用途的產(chǎn)品，可與 RF、IF 和微波無線電應(yīng)用結(jié)合使用。示例包括 AM/FM 調(diào)諧器和接收器、偏置網(wǎng)絡(luò)、基帶處理器、計數(shù)器、數(shù)字可調(diào)電容器、下變頻器、倍頻器、移相器、前置分頻器、端接器、上變頻器、VCO 等。

PRODUCT DESCRIPTION

The AD6650 is a diversity intermediate frequency-to-baseband (IF-to-baseband) receiver for GSM/EDGE. This narrow-band receiver consists of an integrated DVGA, IF-to-baseband I/Q demodulators, low-pass filtering, and a dual wideband ADC. The chip can accommodate IF input from 70 MHz to 260 MHz. The receiver architecture is designed such that only one external surface acoustic wave (SAW) filter for main and one for diversity are required in the entire receive signal path to meet GSM/EDGE blocking requirements.

Digital decimation and filtering circuitry provided on-chip remove unwanted signals and noise outside the channel of interest. Programmable RAM coefficient filters allow antialiasing, matched filtering, and static equalization functions to be combined in a single cost-effective filter. The output of the channel filters is provided to the user via serial output I/Q data streams.

FEATURES

116 dB dynamic range

Digital VGA

I/Q demodulators

Active low-pass filters

Dual wideband ADC

Programmable decimation and channel filters

VCO and phase-locked loop circuitry

Serial data output ports

Intermediate frequencies of 70 MHz to 260 MHz

10 dB noise figure

+43 dBm input IP2 at 70 MHz IF

?9.5 dBm input IP3 at 70 MHz IF

3.3 V I/O and CMOS core

Microprocessor interface

JTAG boundary scan

APPLICATIONS

PHS or GSM/EDGE single carrier, diversity receivers

Microcell and picocell systems

Wireless local loop