AD9643BCPZRL7-210集成電路（IC）的模數(shù)轉(zhuǎn)換器（ADC）規(guī)格書PDF中文資料

AD9643BCPZRL7-210屬于集成電路（IC）的模數(shù)轉(zhuǎn)換器（ADC）。由亞德諾半導(dǎo)體技術(shù)有限公司制造生產(chǎn)的AD9643BCPZRL7-210模數(shù)轉(zhuǎn)換器（ADC）模數(shù)轉(zhuǎn)換器（ADC、A/D 或 A 轉(zhuǎn) D）對模擬信號進行采樣，例如由麥克風(fēng)采集的聲音或傳感器的輸出，然后將其轉(zhuǎn)換為數(shù)字信號。一般來說，數(shù)字輸出是二進制補碼二進制數(shù)，與輸入成比例。輸入類型可能是差分、偽差分或單端輸入。模數(shù)轉(zhuǎn)換器可按照位數(shù)、采樣率、輸入數(shù)、接口、轉(zhuǎn)換器數(shù)和架構(gòu)（例如自適應(yīng)增量、雙斜率、折疊、流水線、SAR、三角積分、兩步式）進行選擇。

GENERAL DESCRIPTION

The AD9643 is a dual, 14-bit analog-to-digital converter (ADC) with sampling speeds of up to 250 MSPS. The AD9643 is designed to support communications applications, where low cost, small size, wide bandwidth, and versatility are desired.

FEATURES

SNR = 70.6 dBFS at 185 MHz AIN and 250 MSPS

SFDR = 85 dBc at 185 MHz AIN and 250 MSPS

?151.6 dBFS/Hz input noise at 185 MHz, ?1 dBFS AIN and

250 MSPS

Total power consumption: 785 mW at 250 MSPS

1.8 V supply voltages

LVDS (ANSI-644 levels) outputs

Integer 1-to-8 input clock divider (625 MHz maximum input)

Sample rates of up to 250 MSPS

IF sampling frequencies of up to 400 MHz

Internal ADC voltage reference

Flexible analog input range

1.4 V p-p to 2.0 V p-p (1.75 V p-p nominal)

ADC clock duty cycle stabilizer

95 dB channel isolation/crosstalk

Serial port control

Energy saving power-down modes

User-configurable, built-in self-test (BIST) capability

APPLICATIONS

Communications

Diversity radio systems

Multimode digital receivers (3G)

TD-SCDMA, WiMax, WCDMA, CDMA2000, GSM, EDGE, LTE

I/Q demodulation systems

Smart antenna systems

General-purpose software radios

Ultrasound equipment

Broadband data applications