ADC1443D開(kāi)發(fā)板套件編程器的評(píng)估板-模數(shù)轉(zhuǎn)換器（ADC）規(guī)格書(shū)PDF中文資料

1. General description

The ADC1443D is a dual channel 14-bit Analog-to-Digital Converter (ADC) with

JESD204B interface (which is backward compatible with the JESD204A interface)

optimized for high dynamic performance and low power consumption at sample rates up

to 185 Msps. Pipelined architecture and output error correction guarantee zero missing

codes over the entire operating range.

Supplied from a single 1.8 V source, the ADC1443D has JESD204B serial outputs over a

configurable number of lanes (1 or 2). Multiple Device Synchronization (MDS) allows

sample-accurate synchronization of the data outputs of multiple ADC devices. It

guarantees a maximum skew of one clock period between as many as 16 output lanes

from up to eight ADC1443D devices.

An integrated Serial Peripheral Interface (SPI) allows easy configuration of the ADC. The

device also includes a programmable full-scale to allow a flexible input voltage range of

1 V (p-p) to 2 V (p-p).

With an analog banwidth from the baseband to input frequencies of up to 1 GHz (typical),

the ADC1443D is ideal for use in undersampled multi-carrier, multistandard

communication system applications.

2. Features and benefits

? Dual channel 14-bit resolution ADC ? SNR = 70.6 dBFS (typical);

fs = 154 Msps; fi

= 190 MHz

? Sampling rate up to 185 Msps ? SFDR = 86 dBc (typical); fs = 154 Msps;

fi

= 190 MHz

? JESD204B Device Subclass 0, 1 and 2

with harmonic clocking and deterministic

latency support

? IMD3 = 88 dBc (typical); fs = 154 Msps;

fi1 = 188.5 MHz; fi2 = 191.5 MHz

? ADC Multiple Device Synchronization

(MDS)

? Analog input bandwidth of 1 GHz

(typical)

? Two JESD204B serial output lanes, up

to 5 Gbps typical

? Pin to pin compatible with ADC1413D

series

? Single 1.8 V supply ? Typical power dissipation = 0.8 W;

fs = 154 Msps

? Offset binary, two’s complement and

Gray output data

? Power-down and sleep modes