C8051F236集成電路（IC）的微控制器規(guī)格書PDF中文資料

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ANALOG PERIPHERALS

Two Comparators

- Programmable Hysteresis

- Configurable to Generate Interrupts or Reset

VDD Monitor and Brown-out Detector

ON-CHIP JTAG DEBUG

- On-Chip Debug Circuitry Facilitates Full Speed, Non-Intrusive In-System Debug (No Emulator Required!)

- Provides Breakpoints, Single Stepping, Watchpoints, Stack Monitor

- Inspect/Modify Memory and Registers

- Superior Performance to Emulation Systems Using ICE-Chips, Target Pods, and Sockets

- Low Cost, Complete Development Kit

SUPPLY VOLTAGE ......................2.7V to 3.6V

- Typical Operating Current: 9mA @ 25MHz

- Typical Stop Mode Current:

Temperature Range: –40°C to +85°C

48-Pin TQFP Package

8051-COMPATIBLE μC Core

- Pipelined Instruction Architecture; Executes 70 of Instructions in 1 or 2 System Clocks

- Up to 25MIPS Throughput with 25MHz Clock

- Expanded Interrupt Handler

MEMORY

- 1280 Bytes Internal Data RAM (256 + 1k)

- 8k Bytes FLASH; In-System Programmable in 512 byte Sectors

DIGITAL PERIPHERALS

- 32 Port I/O; All are 5V tolerant

- Hardware SPITM and UART Serial Ports Available Concurrently

- Three 16-bit Counter/Timers

- Dedicated Watch-Dog Timer

- Bi-directional Reset

CLOCK SOURCES

- Internal Programmable Oscillator: 2-to-16MHz

- External Oscillator: Crystal, RC, C, or Clock

- Can Switch Between Clock Sources on-the-fly; Useful in Power Saving Modes