CD4027BM

CMOS DUAL J-K MASTER-SLAVER FLIP-FLOP

CD4027BM

Dual J-K Master/Slave Flip-Flop with Set and Reset

CD4027BM

CMOS Dual J-K Master-Slave Flip-Flop

CD4027BM

CMOS Dual J-K Master-Slave Flip-Flop

CD4027BM

Package：16-SOIC（0.154"，3.90mm 寬）；包裝：卷帶（TR）剪切帶（CT）Digi-Reel? 得捷定制卷帶 功能：設(shè)置（預(yù)設(shè)）和復(fù)位 類別：集成電路（IC） 觸發(fā)器 描述：IC FF JK TYPE DUAL 1BIT 16SOIC

CD4027BMS

CMOS Dual J-K Master-Slave Flip-Flop

CD4027BMS is a single monolithic chip integrated circuit containing two identical complementary-symmetry J-K masterslave flip-flops. Each flip-flop has provisions for individual J, K, Set Reset, and Clock input signals. Buffered Q and Q signals are provided as outputs. This input-output arrangement ; ? High Voltage Type (20V Rating) \n? Set - Reset Capability \n? Static Flip-Flop Operation - Retains State Indefinitely with Clock Level Either \"High\" or \"Low\" \n? Medium Speed Operation - 16MHz (typ.) Clock Toggle Rate at 10V \n? Standardized Symmetrical Output Characteristics \n? 100% Test;

CD4027BMS

CMOS Dual J-K Master-Slave Flip-Flop

Description CD4027BMSisasinglemonolithicchipintegratedcircuitcontainingtwoidenticalcomplementary-symmetryJ-Kmasterslaveflip-flops.Eachflip-flophasprovisionsforindividualJ,K,SetReset,andClockinputsignals.BufferedQandQsignalsareprovidedasoutputs.Thisinput-out

CD4027BMS

CMOS Dual J-KMaster-Slave Flip-Flop

Features ?HighVoltageType(20VRating) ?Set-ResetCapability ?StaticFlip-FlopOperation-RetainsStateIndefinitely withClockLevelEither“High”or“Low” ?MediumSpeedOperation-16MHz(typ.)ClockToggle Rateat10V ?StandardizedSymmetricalOutputCharacteristics ?100Test

CD4027BM96

CMOS DUAL J-K MASTER-SLAVER FLIP-FLOP

CD4027BM96

CMOS Dual J-K Master-Slave Flip-Flop