CD4076BMS中文資料INTERSIL數(shù)據(jù)手冊PDF規(guī)格書

Description

CD4076BMS types are four-bit registers consisting of D-type flip-flops that feature three-state outputs. Data Disable inputs are provided to control the entry of data into the flip-flops. When both Data Disable inputs are low, data at the D inputs are loaded into their respective flip-flops on the next positive transition of the clock input. Output Disable inputs are also provided. When the Output Disable inputs are both low, the normal logic states of the four outputs are available to the load. The outputs are disabled independently of the clock by a high logic level at either Output Disable input, and present a high impedance.

Features

? High Voltage Type (20V Rating)

? Three State Outputs

? Input Disabled Without Gating the Clock

? Gated Output Control Lines for Enabling or Disabling the Outputs

? Standardized Symmetrical Output Characteristics

? 100 Tested for Quiescent Current at 20V

? Maximum Input Current of 1μA at 18V Over Full Package Temperature Range; 100nA at 18V and +25oC

? Noise Margin (Over Full Package/Temperature Range)

? - 1V at VDD = 5V

? - 2V at VDD = 10V

? - 2.5V at VDD = 15V

? 5V, 10V and 15V Parametric Ratings

? Meets All Requirements of JEDEC Tentative Standard No. 13B, “Standard Specifications for Description of ‘B’ Series CMOS Devices”

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