CD4518B

CMOS雙路BCD（十進(jìn)制）加法計(jì)數(shù)器

CD4518B是雙十進(jìn)制同步加法計(jì)數(shù)器，CD4520B是雙四位二進(jìn)制同步加法計(jì)數(shù)器，二者均是由兩個(gè)相同的、內(nèi)置同步4級計(jì)數(shù)器。每級計(jì)數(shù)器均由D型觸發(fā)器構(gòu)成。由于具有可互換的CLOCK和ENABLE輸入端口，CD4518B/4520B既可由上升沿觸發(fā)也可由下降沿時(shí)觸發(fā)。對于單個(gè)操作來說，ENALBE輸入用來維持高電平，并在每個(gè)CLOCK正向變化時(shí)更新計(jì)數(shù)器。計(jì)數(shù)器在RESET為高電平時(shí)清零。計(jì)數(shù)器實(shí)現(xiàn)在行波模式下的級連，即一個(gè)計(jì)數(shù)器Q4連接到后繼計(jì)數(shù)器的使能輸入端，并且后繼計(jì)數(shù)器的CLOCK輸入端保持低電平。\n\nCD4518B和CD4520B的封裝形式有DIP16和SOP16。;

CD4518B

CMOS 雙路 BCD 加法計(jì)數(shù)器

CD4518 Dual BCD Up-Counter and CD4520 Dual Binary Up-Counter each consist of two identical, internally synchronous 4-stage counters. The counter stages are D-type flip-flops having interchangeable CLOCK and ENABLE lines for incrementing on either the positive-going or negative-going transition. For ; ? Medium-speed operation - ???6-MHz typical clock frequency at 10 V\n? Positive- or negative-edge triggering\n? Synchronous internal carry propagation\n? 100% tested for quiescent current at 20 V\n? Maximum input current of 1 μA at 18 V over full package-temperature range; 100 nA at 18 V and 25°;

CD4518B

CD4000系列 邏輯芯片

CD4518B

CMOS DUAL UP-COUNTERS

CD4518B

CMOS Dual Up-Counters

CD4518B

Cmos Dual Up-Counters

CD4518BMS

CMOS Dual Up Counters

Description CD4518BMSDualBCDUpCounterandCD4520BMSDualBinaryUpCountereachconsistoftwoidentical,internallysynchronous4-stagecounters.ThecounterstagesareD-typeflip-flopshavinginterchangeableCLOCKandENABLElinesforincrementingoneitherthepositive-goingornegative-g

CD4518B_16

Cmos Dual Up-Counters

CD4518BE

CMOS DUAL UP-COUNTERS

CD4518BE

CMOS Dual Up-Counters