CD74ACT10

TRIPLE 3-INPUT POSITIVE-NAND GATES

InputsAreTTL-VoltageCompatible SpeedofBipolarF,AS,andS,With SignificantlyReducedPowerConsumption BalancedPropagationDelays ±24-mAOutputDriveCurrent –Fanoutto15FDevices SCRLatchup-ResistantCMOSProcessand CircuitDesign Exceeds2-kVESDProtectionPer MIL-STD-883,

CD74ACT10

具有 TTL 兼容型 CMOS 輸入的 3 通道、3 輸入、4.5V 至 5.5V 與非門

The CD74ACT10 contains three independent 3-input NAND gates. The device performs the Boolean functions Y = (A ? B ? C)\\ or Y = A\\ + B\\ + C\\ in positive logic.; ? Inputs Are TTL-Voltage Compatible\n? Speed of Bipolar F, AS, and S, With Significantly Reduced Power Consumption\n? Balanced Propagation Delays\n? ±24-mA Output Drive Current \n? Fanout to 15 F Devices\n \n? SCR Latchup-Resistant CMOS Process and Circuit Design\n? Exceeds 2-kV ESD Protection Per M;

CD74ACT10

Triple 3-Input NAND Gate

CD74ACT10

TRIPLE 3-INPUT POSITIVE-NAND GATES

CD74ACT109

DUAL J-K POSITIVE-EDGE-TRIGGERED FLIP-FLOPS WITH CLEAR AND PRESET

InputsAreTTL-VoltageCompatible SpeedofBipolarF,AS,andS,With SignificantlyReducedPowerConsumption BalancedPropagationDelays ±24-mAOutputDriveCurrent –Fanoutto15FDevices SCR-Latchup-ResistantCMOSProcessand CircuitDesign Exceeds2-kVESDProtectionPer MIL-STD-883,

CD74ACT109

具有設(shè)置和復(fù)位端的雙路正邊沿觸發(fā)式 J-K 觸發(fā)器

The ?ACT109 devices contain two independent J-K\\ positive-edge-triggered flip-flops. A low level at the preset (PRE)\\ or clear (CLR)\\ inputs sets or resets the outputs, regardless of the levels of the other inputs. When PRE\\ and CLR\\ are inactive (high), data at the J and K\\ inputs meeting the; ? Inputs Are TTL-Voltage Compatible\n? Speed of Bipolar F, AS, and S, With Significantly Reduced Power Consumption\n? Balanced Propagation Delays\n? ±24-mA Output Drive Current \n? Fanout to 15 F Devices\n \n? SCR-Latchup-Resistant CMOS Process and Circuit Design\n? Exceeds 2-kV ESD Protection Per M;

CD74ACT109E

絲?。?a target="_blank" title="Marking" href="/cd74act109e/marking.html">CD74ACT109E；Package：PDIP；DUAL J-K POSITIVE-EDGE-TRIGGERED FLIP-FLOPS WITH CLEAR AND PRESET

InputsAreTTL-VoltageCompatible SpeedofBipolarF,AS,andS,With SignificantlyReducedPowerConsumption BalancedPropagationDelays ±24-mAOutputDriveCurrent –Fanoutto15FDevices SCR-Latchup-ResistantCMOSProcessand CircuitDesign Exceeds2-kVESDProtectionPer MIL-STD-883,

CD74ACT109E.A

絲印：CD74ACT109E；Package：PDIP；DUAL J-K POSITIVE-EDGE-TRIGGERED FLIP-FLOPS WITH CLEAR AND PRESET

InputsAreTTL-VoltageCompatible SpeedofBipolarF,AS,andS,With SignificantlyReducedPowerConsumption BalancedPropagationDelays ±24-mAOutputDriveCurrent –Fanoutto15FDevices SCR-Latchup-ResistantCMOSProcessand CircuitDesign Exceeds2-kVESDProtectionPer MIL-STD-883,

CD74ACT109M

絲?。?a target="_blank" title="Marking" href="/act109m/marking.html">ACT109M；Package：SOIC；DUAL J-K POSITIVE-EDGE-TRIGGERED FLIP-FLOPS WITH CLEAR AND PRESET

InputsAreTTL-VoltageCompatible SpeedofBipolarF,AS,andS,With SignificantlyReducedPowerConsumption BalancedPropagationDelays ±24-mAOutputDriveCurrent –Fanoutto15FDevices SCR-Latchup-ResistantCMOSProcessand CircuitDesign Exceeds2-kVESDProtectionPer MIL-STD-883,

CD74ACT109M96

絲?。?a target="_blank" title="Marking" href="/act109m/marking.html">ACT109M；Package：SOIC；DUAL J-K POSITIVE-EDGE-TRIGGERED FLIP-FLOPS WITH CLEAR AND PRESET

InputsAreTTL-VoltageCompatible SpeedofBipolarF,AS,andS,With SignificantlyReducedPowerConsumption BalancedPropagationDelays ±24-mAOutputDriveCurrent –Fanoutto15FDevices SCR-Latchup-ResistantCMOSProcessand CircuitDesign Exceeds2-kVESDProtectionPer MIL-STD-883,