CD74HC4094

High Speed CMOS Logic 8-Stage Shift and Store Bus Register, Three-State

Description TheHarrisCD74HC4094andCD74HCT4094are8-stageserialshiftregistershavingastoragelatchassociatedwitheachstageforstrobingdatafromtheserialinputtoparallelbufferedthree-stateoutputs.Theparalleloutputsmaybeconnecteddirectlytocommonbuslines.Dataisshif

CD74HC4094

CDx4HC4094, CD74HCT4094 High-Speed CMOS Logic 8-Stage Shift and Store Bus Register, Three-State

1Features ?Bufferedinputs ?Separateserialoutputssynchronoustoboth positiveandnegativeclockedgesforcascading ?Fanout(overtemperaturerange) –Standardoutputs:10LSTTLloads –Busdriveroutputs:15LSTTLloads ?Wideoperatingtemprange:?55°Cto125°C ?Balancedpropag

CD74HC4094

具有 3 級輸出的高速 CMOS 邏輯 8 級移位和存儲總線寄存器; ? Buffered Inputs\n? Separate Serial Outputs Synchronous to Both Positive and Negative Clock Edges For Cascading\n? Fanout (Over Temperature Range) \n? Standard Outputs. . . . . . . . . . . . . . . 10 LSTTL Loads\n? Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads\n \n? Wide Operating Temperature Range . . . .–55°C to 125°C\n? Balanced Propagation Delay and Transition Times\n? Significant Power Reduction Compared to LSTTL Logic ICs\n? HC Types \n? 2V to 6V Operation\n? High Noise Immunity: NIL = 30%, NIH = 30% of VCC at VCC = 5V\n \n? HCT Types \n? 4.5V to 5.5V Operation\n? Direct LSTTL Input Logic Compatibility, VIL= 0.8V (Max), VIH = 2V (Min)\n? CMOS Input Compatibility, Il ≤ 1μA at VOL, VOH;

The ?HC4094and CD74HCT4094 are 8-stage serial shift registers having a storage latch associated with each stage for strobing data from the serial input to parallel buffered three-stateoutputs. The parallel outputs may be connected directly to common bus lines. Data is shifted on positive clock transitions. The data in each shift register stage is transferred to the storage register when the Strobe input is high. Data in the storage register appears at the outputs whenever the Output-Enable signal is high.\n\n Two serial outputs are available for cascading a number of these devices. Data is available at the QS1 serial output terminal on positive clock edges to allow for high-speed operation in cascaded system in which the clock rise time is fast. The same serial information, available at the QS2 terminal on the next negative clock edge, provides a means for cascading these devices when the clock rise time is slow.

CD74HC4094

HIgh-Speed CMOS Logic 8-Stage Shift and Store Bus Register,Three-State

CD74HC4094

High Speed CMOS Logic 8-Stage Shift and Store Bus Register, Three-State

CD74HC4094

High-Speed CMOS Logic 8-Stage Shift and Store Bus Register, Three-State

CD74HC4094

High-Speed CMOS Logic 8-Stage Shift and Store Bus Register, Three-State

CD74HC4094DYYR

絲?。?a target="_blank" title="Marking" href="/hj4094/marking.html">HJ4094；Package：SOT-23-THIN；CDx4HC4094, CD74HCT4094 High-Speed CMOS Logic 8-Stage Shift and Store Bus Register, Three-State

1Features ?Bufferedinputs ?Separateserialoutputssynchronoustoboth positiveandnegativeclockedgesforcascading ?Fanout(overtemperaturerange) –Standardoutputs:10LSTTLloads –Busdriveroutputs:15LSTTLloads ?Wideoperatingtemprange:?55°Cto125°C ?Balancedpropag

CD74HC4094E

High Speed CMOS Logic 8-Stage Shift and Store Bus Register, Three-State

Description TheHarrisCD74HC4094andCD74HCT4094are8-stageserialshiftregistershavingastoragelatchassociatedwitheachstageforstrobingdatafromtheserialinputtoparallelbufferedthree-stateoutputs.Theparalleloutputsmaybeconnecteddirectlytocommonbuslines.Dataisshif

CD74HC4094E

絲?。?a target="_blank" title="Marking" href="/cd74hc4094e/marking.html">CD74HC4094E；Package：PDIP；CDx4HC4094, CD74HCT4094 High-Speed CMOS Logic 8-Stage Shift and Store Bus Register, Three-State

1Features ?Bufferedinputs ?Separateserialoutputssynchronoustoboth positiveandnegativeclockedgesforcascading ?Fanout(overtemperaturerange) –Standardoutputs:10LSTTLloads –Busdriveroutputs:15LSTTLloads ?Wideoperatingtemprange:?55°Cto125°C ?Balancedpropag