CDB53L21開發(fā)板套件編程器的評估板-模數(shù)轉(zhuǎn)換器（ADC）規(guī)格書PDF中文資料

CDB53L21屬于開發(fā)板套件編程器的評估板-模數(shù)轉(zhuǎn)換器（ADC）。由凌云邏輯制造生產(chǎn)的CDB53L21評估板 - 模數(shù)轉(zhuǎn)換器（ADC）模數(shù)轉(zhuǎn)換器 (ADC) 評估板是預(yù)裝有元器件的電路板，用于提供特定 ADC 或器件工作實(shí)例。特定板上的 A/D 轉(zhuǎn)換器數(shù)量從 3 到 32 不等，每秒采樣率從 2.5 kHz 到 26 GHz 不等，輸入電壓范圍從 0 到 8 Vp-p。

GENERAL DESCRIPTION

The CS53L21 is a highly integrated, 24-bit, 96 kHz, low power stereo A/D. Based on multi-bit, delta-sigma modulation, it allows infinite sample rate adjustment between 4 kHz and 96 kHz. The ADC offers many fea tures suitable for low power, portable system applications.

FEATURES

? 98 dB Dynamic Range (A-wtd)

? -88 dB THD+N

? Analog Gain Controls

– +32 dB or +16 dB MIC Pre-Amplifiers

– Analog Programmable Gain Amplifier (PGA)

? +20 dB Digital Boost

? Programmable Automatic Level Control (ALC)

– Noise Gate for Noise Suppression

– Programmable Threshold and Attack/Release Rates

? Independent Left/Right Channel Control

? Digital Volume Control

? High-Pass Filter Disable for DC Measurements

? Stereo 3:1 Analog Input MUX

? Dual MIC Inputs

– Programmable, Low Noise MIC Bias Levels

– Differential MIC Mix for Common Mode Noise Rejection

? Very Low 64 Fs Oversampling Clock Reduces Power Consumption

SYSTEM FEATURES

? 24-bit Conversion

? 4 kHz to 96 kHz Sample Rate

? Multi-bit Delta Sigma Architecture

? Low Power Operation

– Stereo Record (ADC): 8.72 mW @ 1.8 V

– Stereo Record (MIC to PGA and ADC): 13.73 mW @ 1.8 V

? Variable Power Supplies

– 1.8 V to 2.5 V Digital & Analog

– 1.8 V to 3.3 V Interface Logic

? Power Down Management

– ADC, MIC Pre-Amplifier, PGA

? Software Mode (I2C? & SPI? Control)

? Hardware Mode (Stand-Alone Control)

? Flexible Clocking Options

– Master or Slave Operation

? Digital Routing Mixes

– Mono Mixes

APPLICATIONS

? Portable Audio Players

? Digital Microphones

? Digital Voice Recorders

? Voice Recognition Systems

? Audio/Video Capture Cards