CDCVF2509A

具有斷電模式的 3.3V 鎖相環(huán)路時(shí)鐘驅(qū)動(dòng)器

The CDCVF2509A is a high-performance, low-skew, low-jitter, phase-lock loop (PLL) clock driver. It uses a PLL to precisely align, in both frequency and phase, the feedback (FBOUT) output to the clock (CLK) input signal. It is specifically designed for use with synchronous DRAMs. The CDCVF2509A opera; ? Designed to Meet and Exceed PC133 SDRAM Registered DIMM Specification Rev. 1.1\n? Spread Spectrum Clock Compatible\n? Operating Frequency 20 MHz to 175 MHz\n? Static Phase Error Distribution at 66 MHz to 166 MHz Is ±125 ps\n? Jitter (cyc - cyc) at 60 MHz to 175 MHz Is Typ = 65 ps\n? Advanced Deep;

CDCVF2509A

3.3-V PHASE-LOCK LOOP CLOCK DRIVER WITH POWER DOWN MODE

CDCVF2509A

3.3-V PHASE-LOCK LOOP CLOCK DRIVER WITH POWER DOWN MODE

CDCVF2509A_15

3.3-V PHASE-LOCK LOOP CLOCK DRIVER WITH POWER DOWN MODE

CDCVF2509APW

3.3-V PHASE-LOCK LOOP CLOCK DRIVER WITH POWER DOWN MODE

CDCVF2509APW

3.3-V PHASE-LOCK LOOP CLOCK DRIVER WITH POWER DOWN MODE

CDCVF2509APWG4

3.3-V PHASE-LOCK LOOP CLOCK DRIVER WITH POWER DOWN MODE

CDCVF2509APWR

3.3-V PHASE-LOCK LOOP CLOCK DRIVER WITH POWER DOWN MODE

CDCVF2509APWR

3.3-V PHASE-LOCK LOOP CLOCK DRIVER WITH POWER DOWN MODE

CDCVF2509APWRG4

3.3-V PHASE-LOCK LOOP CLOCK DRIVER WITH POWER DOWN MODE