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CDP1854AD中文資料Intersil數(shù)據(jù)手冊PDF規(guī)格書

CDP1854AD
廠商型號

CDP1854AD

功能描述

Programmable Universal Asynchronous Receiver/Transmitter (UART)

文件大小

95.46 Kbytes

頁面數(shù)量

21

生產(chǎn)廠商 Intersil Corporation
企業(yè)簡稱

Intersil

中文名稱

Intersil Corporation官網(wǎng)

原廠標識
數(shù)據(jù)手冊

下載地址一下載地址二到原廠下載

更新時間

2025-1-26 16:30:00

CDP1854AD規(guī)格書詳情

Description

The CDP1854A and CDP1854AC are silicon-gate CMOS Universal Asynchronous Receiver/Transmitter (UART) circuits. They are designed to provide the necessary formatting and control for interfacing between serial and parallel data. For example, these UARTs can be used to interface between a peripheral or terminal with serial I/O ports and the 8-bit CDP1800-series microprocessor parallel data bus system. The CDP1854A is capable of full duplex operation, i.e., simultaneous conversion of serial input data to parallel output data and parallel input data to serial output data.

Features

? Two Operating Modes

??? - Mode 0 - Functionally Compatible with Industry Types Such as the TR1602A and CDP6402

??? - Mode 1 - Interfaces Directly with CDP1800-Series Microprocessors without Additional Components

? Full or Half Duplex Operation

? Parity, Framing and Overrun Error Detection

? Baud Rate

??? - DC to 200K Bits/s at VDD . . . . . . . . . . . . . . . . . . . . 5V

??? - DC to 400K Bits/s at VDD . . . . . . . . . . . . . . . . . . . . 10V

? Fully Programmable with Externally Selectable Word Length (5-8 Bits), Parity Inhibit, Even/Odd Parity, and 1, 1-1/2, or 2 Stop Bits

? False Start Bit Detection

產(chǎn)品屬性

  • 型號:

    CDP1854AD

  • 制造商:

    INTERSIL

  • 制造商全稱:

    Intersil Corporation

  • 功能描述:

    Programmable Universal Asynchronous Receiver/Transmitter(UART)

供應商 型號 品牌 批號 封裝 庫存 備注 價格
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6
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25000
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2
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589220
16余年資質(zhì) 絕對原盒原盤 更多數(shù)量
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23+
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5000
原裝正品,假一罰十
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2020+
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80000
只做自己庫存,全新原裝進口正品假一賠百,可開13%增
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HARRIS
18+
DIP40
85600
保證進口原裝可開17%增值稅發(fā)票
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23+
原廠正規(guī)渠道
5000
專注配單,只做原裝進口現(xiàn)貨
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H
18
CDIP
200
進口原裝正品優(yōu)勢供應
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HAR
2020+
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4500
百分百原裝正品 真實公司現(xiàn)貨庫存 本公司只做原裝 可
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