CL-PS7111-VC-A中文資料凌云邏輯數(shù)據(jù)手冊(cè)PDF規(guī)格書

OVERVIEW

The CL-PS7111 is designed for ultra-low-power applications such as organizers/PDAs, two-way pagers, smart phones, and hand-held internet appliances. The core-logic functionality of the device is built around an ARM710a microprocessor with 8 Kbytes of four-way set-associative unified cache.

FEATURES

■ Ultra low power

— Designed for applications that require long battery life while using standard AA/AAA batteries

— Average 45 mW/66 mW in normal operation (2.7 V/3.3 V, 13 MHz/18.432 MHz)

— Average 15 mW in idle mode (clock to the CPU stopped, everything else running)

— Average 15 μA in standby mode (realtime clock on, everything else stopped)

■ Performance matching 33-MHz Intel? ’486-based PC

— 15 Vax?-MIPS (Dhrystone?) at 18 MHz

■ ARM710a microprocessor

— ARM7 CPU

— 8 Kbytes of four-way set-associative cache

— MMU with 64-entry TLB (transition look-aside buffer)

■ DRAM controller

— Supports both 16- and 32-bit-wide DRAMs

■ ROM/SRAM/flash memory control

— Decodes 4, 5, or 6 separate memory segments of 256 Mbytes

— Each segment can be configured as 8, 16, or 32 bits wide and support page-mode access — Programmable access time for conventional SRAM/ROM/flash memory

■ Support for up to two ultra-low-power CL-PS6700 PC Card controllers

■ 2 Kbytes of on-chip SRAM for fast program execution

■ On-chip boot ROM

■ Two synchronous serial interfaces

— Supports SPI?1 or Microwire?2-compatible

— Audio codec

■ 27-bit general-purpose I/O

— Three 8-bit and one 3-bit GPIO port

— Supports scanning keyboard matrix

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