CS2100-OTP中文資料凌云邏輯數(shù)據(jù)手冊PDF規(guī)格書

General Description

The CS2100-OTP is an extremely versatile system clocking device that utilizes a programmable phase lock loop. The CS2100-OTP is based on a hybrid analogdigital PLL architecture comprised of a unique combination of a Delta-Sigma Fractional-N Frequency Synthesizer and a Digital PLL. This architecture allows for generation of a low-jitter clock relative to an external noisy synchronization clock with frequencies as low as 50 Hz. The CS2100-OTP has many configuration options which are set once prior to runtime. At runtime there are three hardware configuration pins available for mode and feature selection.

Features

? Clock Multiplier / Jitter Reduction

– Generates a Low Jitter 6 - 75 MHz Clock from a Jittery or Intermittent 50 Hz to 30 MHz Clock Source

? Highly Accurate PLL Multiplication Factor

– Maximum Error Less Than 1 PPM in High-Resolution Mode

? One-Time Programmability

– Configurable Hardware Control Pins

– Configurable Auxiliary Output

? Flexible Sourcing of Reference Clock

– External Oscillator or Clock Source

– Supports Inexpensive Local Crystal

? Minimal Board Space Required

– No External Analog Loop-filter Components