CS8952T中文資料凌云邏輯數(shù)據(jù)手冊PDF規(guī)格書

DESCRIPTION

The CS8952T uses CMOS technology to deliver a high-performance, low-cost 100BASE-X/10BASE-T Physical Layer (PHY) line interface. It makes use of an adaptive equalizer optimized for noise and near end crosstalk (NEXT) immunity to extend receiver operation to cable lengths exceeding 160 m. In addition, the transmit circuitry has been designed to provide extremely low transmit jitter (

FEATURES

■ Single-Chip IEEE 802.3 Physical Interface IC for 100BASE-TX and 10BASE-T

■ Adaptive Equalizer provides Extended Length Operation with Superior Noise Immunity and NEXT Margin

■ Extremely Low Transmit Jitter (<400 ps)

■ Low Common Mode Noise on TX Driver for Reduced EMI Problems

■ Integrated RX and TX Filters for 10BASE-T

■ Compensation for Back-to-Back “Killer Packets”

■ Digital Interfaces Supported

— Media Independent Interface (MII) for 100BASE-X and 10BASE-T

— Repeater 5-bit code-group interface (100BASE-X)

— 10BASE-T Serial Interface

■ Register Set Compatible with DP83840A

■ IEEE 802.3 Auto-Negotiation with Next Page Support

■ Six LED drivers (LNK, COL, FDX, TX, RX, and SPD)

■ Low power (135 mA Typical) CMOS design operates on a single 5 V supply