CV141中文資料瑞薩數(shù)據(jù)手冊PDF規(guī)格書

FEATURES:

? Compliant with Intel DB800 spec

? Eight differential clock pairs at 0.7V

? 50ps skew

? 50ps cycle-to-cycle jitter

? Programmable Bandwidth

? PLL bypass configurable

? Divide by 2 programmable

? Available in SSOP and TSSOP packages

DESCRIPTION:

The CV141 differential buffer is compliant with Intel DB800 specifications. It

is intended to distribute the SRC (serial reference clock) as a companion chip

to the main clock of the CK409, CK410/CK410M, CK410B, etc. PLL is off in

bypass mode and has no clock detect.