CX50561中文資料etc未分類(lèi)制造商數(shù)據(jù)手冊(cè)PDF規(guī)格書(shū)

[ChipX Inc.]

Product Description

The 0.18um CX5000 is an ASIC that utilizes the combination of an advanced metal programmable gate array and optimized EDA system to implement high performance ASIC designs while reducing application tooling costs and design turnaround time. ASIC designers using the CX5000 are able to meet or exceed their design schedules and budgets without compromising technical objectives.

Key Features and Benefits

? Structured ASIC architecture

? Low NRE and start-up costs

? Fast time to production

? 30K to 1.2M usable ASIC gates

? Up to 2.6M bits of fast block memory

? 2ns access time single-port SRAM, dual-port SRAM and ROM

? Low power consumption (0.06uW/MHz/Gate)

? 200MHz general core logic operation, 650MHz in constrained clock domains

? PCI, PCI-X, SSTL, HSTL, USB1.1, RSDS, LVPECL and LVDS up to 622Mbps

? 1.5V or 1.8V or mixed supply voltage operation

? Up to 1100 total pads

? Low-jitter analog PLL macros with internal loop filter

? Delay Lock Loop (DLL) macros for clock de-skewing

? Wide range of synthesizable IP cores such as CPUs and interface controllers

? Vast packaging library

? Standard ASIC tool flow

? Available front-end and FPGA conversion design services

? BIST and Scan synthesis test options

? Seamless migration to Standard Cell in high volume

? Excellent for SoC designs, new ASICs, and FPGA conversion