DS80C400中文資料亞德諾數(shù)據(jù)手冊(cè)PDF規(guī)格書(shū)

GENERAL DESCRIPTION

The DS80C400 is a fast 8051-compatible microcontroller that executes instructions up to three times faster than an original 8051 at the same crystal speed. Its maximum system-clock frequency of 75MHz results in a minimum instruction cycle time of 54ns. Access to large program or data memory areas is simplified with a 24-bit addressing scheme that supports up to 16MB of flat memory. To accelerate data transfers between the microcontroller and the 16MB memory map, the DS80C400 provides four data pointers, each of which can be configured to automatically increment or decrement upon execution of certain data pointer-related instructions. The mircocontroller’s hardware math accelerator further increases the speed of 32-bit and 16-bit multiply and divide operations as well as high-speed shift, normalization, and accumulate functions.

FEATURES

■ High-Performance Architecture

― Single 8051 instruction cycle in 54ns

― DC to 75MHz clock rate

― Flat 16MB address space

― Four data pointers with auto-increment/decrement and select-accelerate data movement

― 16/32-bit math accelerator

■ Multitiered Networking and I/O

― 10/100 Ethernet media access controller (MAC)

― CAN 2.0B controller

― 1-Wire? net controller

― Three full-duplex hardware serial ports

― Up to eight bidirectional 8-bit ports (64 digital I/O pins)

■ Robust ROM Firmware

― Supports network boot over Ethernet using DHCP and TFTP

― Full, application-accessible TCP/IP network stack

― Supports IPv4 and IPv6

― Implements UDP, TCP, DHCP, ICMP, and IGMP

― Preemptive, priority-based task scheduler

― MAC address can optionally be acquired from IEEE-registered DS2502-E48

■ 10/100 Ethernet MAC

― Flexible IEEE 802.3 MII (10/100Mbps) and ENDEC (10Mbps) interfaces allow selection of PHY

― Low-power operation

― Ultra-low-power sleep mode with Magic Packet? and wake-up frame detection

― 8kB on-chip Tx/Rx packet data memory with buffer control unit reduces load on CPU

― Half- or full-duplex operation with flow control

― Multicast/broadcast address filtering with VLAN support

■ Full-Function CAN 2.0B Controller

― 15 message centers

― Supports standard (11-bit) and extended (29-bit) identifiers and global masks

― Media byte filtering to support DeviceNet?, SDS, and higher layer CAN protocols

― Auto-baud mode and SIESTA low-power mode

■ Integrated Primary System Logic

― 16 total interrupt sources with 6 external

― Four 16-bit timer/counters

― 2X/4X clock multiplier reduces electromagnetic interference (EMI)

― Programmable watchdog timer

― Oscillator-fail detection

― Programmable IrDA clock

■ Advanced Power Management

― Energy saving 1.8V Core

― 3.3V I/O operation, 5V tolerant

― Power-management, idle, and stop mode operations with switchback feature

― Ethernet and CAN shutdown control for power conservation

― Early warning power-fail interrupt

― Power-fail reset

■ Enhanced Memory Architecture

― Selectable 8/10-bit stack pointer for highlevel language support

― 1kB additional on-chip SRAM usable as stack/data memory

― 16-bit/24-bit paged/24-bit contiguous modes

― Selectable multiplexed/nonmultiplexed external memory interface

― Merged program/data memory space allows in-system programming

― Defaults to true 8051 memory compatibility

APPLICATIONS

■ Industrial Control/Automation

■ Vending

■ Data Converters (Serial-to-Ethernet)

■ Data Collection Equipment

■ Environmental Monitoring

■ Home/Office Automation

■ Transaction/Payment Terminals