DS99R101

3-40MHz 直流平衡 24 位 LVDS 串行器

The DS99R101/DS99R102 Chipset translates a 24-bit parallel bus into a fully transparent data/control LVDS serial stream with embedded clock information. This single serial stream simplifies transferring a 24-bit bus over PCB traces and cable by eliminating the skew problems between parallel data and; ? 3 MHz–40 MHz Clock Embedded and DC-Balancing 24:1 and 1:24 Data Transmissions\n? User Selectable Clock Edge for Parallel Data on Both Transmitter and Receiver \n? Internal DC Balancing Encode/Decode – Supports AC-Coupling Interface with No External Coding Required\n? Individual Power-Down Controls;

DS99R101

3-40MHz DC-Balanced 24-Bit LVDS Serializer and Deserializer

DS99R101

DS99R101/DS99R102 3-40MHz DC-Balanced 24-Bit LVDS Serializer and Deserializer

DS99R101

3-40MHz DC-Balanced 24-Bit LVDS Serializer and Deserializer

DS99R101_13

DS99R101/DS99R102 3-40MHz DC-Balanced 24-Bit LVDS Serializer and Deserializer

DS99R101_14

3-40MHz DC-Balanced 24-Bit LVDS Serializer and Deserializer

DS99R101VS

3-40MHz DC-Balanced 24-Bit LVDS Serializer and Deserializer

DS99R101VS/NOPB

DS99R101/DS99R102 3-40MHz DC-Balanced 24-Bit LVDS Serializer and Deserializer

DS99R101VSSLASHNOPB

DS99R101/DS99R102 3-40MHz DC-Balanced 24-Bit LVDS Serializer and Deserializer

DS99R101VSX

3-40MHz DC-Balanced 24-Bit LVDS Serializer and Deserializer