首頁>EPM570Z>規(guī)格書詳情

EPM570Z集成電路（IC）的CPLD（復雜可編程邏輯器件）規(guī)格書PDF中文資料

廠商型號	EPM570Z
參數(shù)屬性	EPM570Z 封裝/外殼為100-TFBGA；包裝為托盤；類別為集成電路（IC）的CPLD（復雜可編程邏輯器件）；產(chǎn)品描述：IC CPLD 440MC 9NS 100MBGA
功能描述	Section I. MAX II Device Family
封裝外殼	100-TFBGA
文件大小	987.8 Kbytes
頁面數(shù)量	88 頁
生產(chǎn)廠商	Altera Corporation
企業(yè)簡稱	Altera【阿爾特】
中文名稱	阿爾特拉公司官網(wǎng)
原廠標識
數(shù)據(jù)手冊	下載地址一下載地址二到原廠下載
更新時間	2025-1-26 19:28:00

Features

The MAX II CPLD has the following features:

■ Low-cost, low-power CPLD

■ Instant-on, non-volatile architecture

■ Standby current as low as 25 μA

■ Provides fast propagation delay and clock-to-output times

■ Provides four global clocks with two clocks available per logic array block (LAB)

■ UFM block up to 8 Kbits for non-volatile storage

■ MultiVolt core enabling external supply voltages to the device of either

3.3 V/2.5 V or 1.8 V

■ MultiVolt I/O interface supporting 3.3-V, 2.5-V, 1.8-V, and 1.5-V logic levels

■ Bus-friendly architecture including programmable slew rate, drive strength,

bus-hold, and programmable pull-up resistors

■ Schmitt triggers enabling noise tolerant inputs (programmable per pin)

■ I/Os are fully compliant with the Peripheral Component Interconnect Special

Interest Group (PCI SIG) PCI Local Bus Specification, Revision 2.2 for 3.3-V

operation at 66 MHz

■ Supports hot-socketing

■ Built-in Joint Test Action Group (JTAG) boundary-scan test (BST) circuitry

compliant with IEEE Std. 1149.1-1990

■ ISP circuitry compliant with IEEE Std. 1532