ESP32-C5NF4中文資料樂鑫科技數(shù)據(jù)手冊PDF規(guī)格書

Features

Wi-Fi

? 1T1R in 2.4 and 5 GHz dual band

? Operating frequency: 2412 ~ 2484 MHz, 5180 ~ 5885 MHz

? IEEE 802.11ax-compliant

– 20 MHz-only non-AP mode

– Uplink and downlink OFDMA to enhance connectivity and performance in congested environments

for IoT applications

– Downlink MU-MIMO (multi-user, multiple input, multiple output) to increase network capacity

– Beamformee that improves signal quality

– Spatial reuse to maximize parallel transmissions

– Target wake time (TWT) that optimizes power saving mechanisms

? IEEE 802.11ac-compliant

– 20 MHz bandwidth

– Downlink fullband MU-MIMO

? Fully compatible with IEEE 802.11a/b/g/n protocol

– 20 MHz and 40 MHz bandwidth

– Data rate up to 150 Mbps

– Wi-Fi Multimedia (WMM)

– TX/RX A-MPDU, TX/RX A-MSDU

– Immediate Block ACK

– Fragmentation and defragmentation

– Transmission opportunity (TXOP)

– Automatic Beacon monitoring (hardware TSF)

– Four virtual Wi-Fi interfaces

– Simultaneous support for Infrastructure BSS in Station mode, SoftAP mode, Station + SoftAP mode,

and promiscuous mode

Note that when ESP32-C5 scans in Station mode, the SoftAP channel will change along with the

Station channel

– Antenna diversity

– 802.11mc FTM

Bluetooth?

? Bluetooth LE: Bluetooth Core 6.0 certified

? Bluetooth mesh 1.1

? High power mode (20 dBm)

? Direction finding (AoA/AoD)

? Periodic advertising with responses (PAwR)

? LE connection subrating

? LE power control

? Speed: 125 Kbps, 500 Kbps, 1 Mbps, 2 Mbps

? LE advertising extensions and multiple advertising sets

? Allow devices to operate in Broadcaster, Observer, Central, and Peripheral roles concurrently

IEEE 802.15.4

? Compliant with IEEE 802.15.4-2015 protocol

? OQPSK PHY in 2.4 GHz band

? Data rate: 250 Kbps

? Thread 1.4

? Zigbee 3.0

CPU and Memory

? High-performance (HP) RISC-V processor:

– Clock speed: up to 240 MHz

– Five-stage pipeline

– CoreMark? score: 820.19 CoreMark；3.42 CoreMark/MHz (O3)

? Low-power (LP) RISC-V processor:

– Clock speed: up to 40 or 48 MHz

– Two-stage pipeline

? ROM: 320 KB

? HP SRAM: 384 KB

? LP SRAM: 16 KB

? Flash/PSRAM controller with cache is supported

? Flash in-circuit programming (ICP) is supported

Advanced Peripheral Interfaces

? 29 GPIOs

? Analog interfaces:

– 12-bit SAR ADC, up to 6 channels

– Temperature sensor

– Brownout detector

– Analog voltage comparator