HCS166KMSR中文資料Intersil數(shù)據(jù)手冊(cè)PDF規(guī)格書

Description

The Intersil HCS166MS is an 8-bit shift register that has fully synchronous serial or parallel data entry selected by an active LOW Parallel Enable (PE) input. When the PE is LOW one setup time before the LOW-to-HIGH clock transition, parallel data is entered into the register. When PE is HIGH, data is entered into internal bit position Q0 from Serial Data Input (DS), and the remaining bits are shifted one place to the right (Q0 → Q1 → Q2m etc.) with each positive-going clock transition. For expansion of the register in parallel to serial converters, the Q7 output is connected to the DS input of the succeeding stage.

Features

? 3 Micron Radiation Hardened CMOS SOS

? Total Dose 200K RAD (Si)

? SEP Effective LET No Upsets: >100 MEV-cm2/mg

? Single Event Upset (SEU) Immunity < 2 x 10-9 Errors/Bit-Day (Typ)

? Dose Rate Survivability: >1 x 1012 RAD (Si)/s

? Dose Rate Upset >1010 RAD s(Si)/s 20ns Pulse

? Latch-Up Free Under Any Conditions

? Fanout (Over Temperature Range)

- Standard Outputs - 10 LSTTL Loads

? Military Temperature Range: -55°C to +125°C

? Significant Power Reduction Compared to LSTTL ICs

? DC Operating Voltage Range: 4.5V to 5.5V

? Input Logic Levels

??? - VIL = 0.3 VCC Max

??? - VIH = 0.7 VCC Min

? Input Current Levels Ii ≤ 5μA at VOL, VOH