IDTCV110JP中文資料IDT數(shù)據(jù)手冊(cè)PDF規(guī)格書(shū)

DESCRIPTION:

IDTCV110J is a 56 pin clock device. The CPU output buffer is designed to support up to 400MHz processor. This chip has three PLLs inside for CPU/SRC/PCI, SATA, and 48MHz/DOT96 IO clocks. One dedicated PLL for Serial ATA clock provides high accuracy frequency. This device also implements Band-gap referenced IREF to reduce the impact of VDD variation on differential outputs, which can provide more robust system performance.

Static PLL frequency divide error can be as low as 36 ppm, worse case 114 ppm, providing high accuracy output clock. Each CPU/SRC/PCI, SATA clock has its own Spread Spectrum selection, which allows for isolated changes instead of affecting other clock groups.

FEATURES:

? One high precision PLL for CPU, SSC, and N programming

? One high precision PLL for SRC/PCI/SATA, SSC, and N programming

? One high precision PLL for 96MHz/48MHz

? Band-gap circuit for differential outputs

? Support spread spectrum modulation, down spread 0.5

? Support SMBus block read/write, index read/write

? Selectable output strength for REF

? Allows for CPU frequency to change to a higher frequency for maximum system computing power

? Available in SSOP package