IDTV105A集成電路（IC）的驅動器接收器收發(fā)器規(guī)格書PDF中文資料

Features

? Dual 32+3-bit LVTTL input supports up to 150 MHz pixel

rate.

? Dual pixel, LVDS output supports 150 MHz pixel rate

(compatible with 1080p and WUXGA resolution)

? Internal PLL requires no external loop filter

? Selectable rising or falling clock edge for data alignment

? Compatible with Spread Spectrum clock source

? Reduced LVDS output voltage swing mode (selectable)

to minimize EMI

? Single 3.3 V supply

? Low power consumption CMOS design

? Power down mode

? Available in 144 pin LQFP package (14x14mm body size)