ISP1161A1BM中文資料飛利浦?jǐn)?shù)據(jù)手冊(cè)PDF規(guī)格書(shū)

General description

The ISP1161A1 is a single-chip Universal Serial Bus (USB) Host Controller (HC) and Device Controller (DC). The Host Controller portion of the ISP1161A1 complies with Universal Serial Bus Specification Rev. 2.0,supporting data transfer at full-speed (12 Mbit/s) and low-speed (1.5 Mbit/s). The Device Controller portion of the ISP1161A1 also complies withUniversal Serial Bus Specification Rev. 2.0, supporting data transfer at full-speed (12 Mbit/s). These two USB controllers, the HC and the DC, share the same microprocessor bus interface. They have the same data bus, but different I/O locations. They also have separate interrupt request output pins,

separate DMA channels that include separate DMA request output pins and DMA acknowledge input pins. This makes it possible for a microprocessor to control both the USB HC and the USB DC at the same time.

Features

■Complies withUniversal Serial Bus Specification Rev. 2.0

■The Host Controller portion of the ISP1161A1 supports data transfer at full-speed (12 Mbit/s) and low-speed (1.5 Mbit/s)

■The Device Controller portion of the ISP1161A1 supports data transfer at full-speed (12 Mbit/s)

■Combines the HC and the DC in a single chip

■On-chip DC complies with most USB device class specifications

■Both the HC and the DC can be accessed by an external microprocessor via separate I/O port addresses

■Selectable one or two downstream ports for the HC and one upstream port for the DC

■High-speed parallel interface to most of the generic microprocessors and Reduced Instruction Set Computer (RISC) processors such as:

◆Hitachi? SuperH? SH-3 and SH-4

◆MIPS-based? RISC

◆ARM7?, ARM9?, StrongARM?

■Maximum 15 Mbyte/s data transfer rate between the microprocessor and the HC, 11.1 Mbyte/s data transfer rate between the microprocessor and the DC

■Supports single-cycle and burst mode DMA operations

■Up to 14 programmable USB endpoints with 2 fixed control IN/OUT endpoints for the DC

■Built-in separate FIFO buffer RAM for the HC (4 kbytes) and DC (2462 bytes)

■Endpoints with double buffering to increase throughput and ease real-time data transfer for both DC transfers and HC isochronous (ISO) transactions

■6 MHz crystal oscillator with integrated PLL for low EMI

■Controllable LazyClock (100 kHz±50 ) output during ‘suspend’

■Clock output with programmable frequency (3 MHz to 48 MHz)

■Software controlled connection to USB bus (SoftConnect) on upstream port for the DC

■Good USB connection indicator that blinks with traffic (GoodLink) for the DC

■Software selectable internal 15 k?pull-down resistors for HC downstream ports

■Dedicated pins for suspend sensing output and wake-up control input for flexible applications

■Global hardware reset input pin and separate internal software reset circuits for HC and DC

■Operation from a 5 V or a 3.3 V power supply

■Operating temperature range?40°Cto+85°C

■Available in two LQFP64 packages (SOT314-2 and SOT414-1).

Applications

■Personal Digital Assistant (PDA)

■Digital camera

■Third-generation (3-G) phone

■Set-Top Box (STB)

■Information Appliance (IA)

■Photo printer

■MP3 jukebox

■Game console.