LSF0002中文資料德州儀器數(shù)據(jù)手冊PDF規(guī)格書

1 Features

? Provides bidirectional voltage translation with no

direction pin

? Supports up to 100MHz up translation and greater

than 100MHz down translation at

≤ 30pF capacitive load and up To 40MHz up or

down translation at 50pF capacitive load

? Allows bidirectional voltage-level translation

between

– 0.95V ? 1.8/2.5/3.3/5V

– 1.2V ? 1.8/2.5/3.3/5V

– 1.8V ? 2.5/3.3/5V

– 2.5V ? 3.3/5V

– 3.3V ? 5V

? Low standby current

? 5V tolerance I/O port to support TTL

? Low RON provides less signal distortion

? High-impedance I/O pins for EN = Low

? Flow-through pinout for easy PCB trace routing

? Latch-up performance >100mA per JESD 17

? –40°C to 125°C operating temperature range

2 Applications

? GPIO, MDIO, PMBus, SMBus, SDIO, UART, I2C,

and other interfaces in telecom infrastructure

? Enterprise systems

? Communications equipment

? Personal electronics

? Industrial applications

3 Description

The LSF0002 supports bidirectional voltage

translation without the need for DIR pin, which

minimizes system effort (for PMBus, I2C, SMBus, and

so forth). The LSF family of devices supports up

to 100MHz up translation and greater than 100MHz

down translation at ≤ 30pF capacitive load and up

to 40MHz up or down translation at 50pF capacitive

load, which allows the LSF family to support more

consumer or telecom interfaces (MDIO or SDIO).

LSF family supports 5V tolerance on I/O port, which

makes it compatible with TTL levels in industrial and

telecom applications. The LSF family can set up

different voltage translation levels, which makes it

very flexible.

Unlike the LSF0x0x family, the LSF0002 does not

require VREF_A and VREF_B power supplies and the

200kΩ bias resistor. The LSF0002 utilizes the VBIAS

pin that enables translation by being biased to the

same voltage as the lower power supply at the I/Os

that is being translated to and from.