MC14518BDWR2集成電路（IC）的計(jì)數(shù)器除法器規(guī)格書PDF中文資料

MC14518BDWR2屬于集成電路（IC）的計(jì)數(shù)器除法器。由安森美半導(dǎo)體公司制造生產(chǎn)的MC14518BDWR2計(jì)數(shù)器，除法器計(jì)數(shù)器和除法器 IC 是數(shù)字邏輯器件，可對(duì)輸入發(fā)生的邏輯轉(zhuǎn)換進(jìn)行計(jì)數(shù)，然后使用多個(gè)并行輸出重新發(fā)送累加的計(jì)數(shù)，和/或生成單個(gè)輸出信號(hào)轉(zhuǎn)換，從而對(duì)應(yīng)用某些整數(shù)數(shù)量輸入信號(hào)轉(zhuǎn)換進(jìn)行響應(yīng)。除了簡(jiǎn)單的事件計(jì)數(shù)，它們還可用于各種頻率合成應(yīng)用。

The MC14518B dual BCD counter and the MC14520B dual binary counter are constructed with MOS P?channel and N?channel enhancement mode devices in a single monolithic structure. Each consists of two identical, independent, internally synchronous 4?stage counters. The counter stages are type D flip?flops, with interchangeable Clock and Enable lines for incrementing on either the positive?going or negative?going transition as required when cascading multiple stages. Each counter can be cleared by applying a high level on the Reset line. In addition, the MC14518B will count out of all undefined states within two clock periods. These complementary MOS up counters find primary use in multi?stage synchronous or ripple counting applications requiring low power dissipation and/or high noise immunity.

Features

? Diode Protection on All Inputs

? Supply Voltage Range = 3.0 Vdc to 18 Vdc

? Internally Synchronous for High Internal and External Speeds

? Logic Edge?Clocked Design — Incremented on Positive Transition of Clock or Negative Transition on Enable

? Capable of Driving Two Low?power TTL Loads or One Low?power

Schottky TTL Load Over the Rated Temperature Range

? Pb?Free Packages are Available*