MC1650中文資料摩托羅拉數(shù)據(jù)手冊(cè)PDF規(guī)格書(shū)

The MC1650 and the MC1651 are very high speed comparators utilizing differential amplifier inputs to sense analog signals above or below a reference level. An output latch provides a unique sample-hold feature. The MC1650 provides high impedance Darlington inputs, while the MC1651 is a lower impedance option, with higher input slew rate and higher speed capability.

The clock inputs (Ca and Cb) operate from MECL III or MECL 10,000 digital levels. When C a is at a logic high level, Q0 will be at a logic high level provided that V1 > V2 (V1 is more positive than V2). Q0 is the logic complement of Q0. When the clock input goes to a low logic level, the outputs are latched in their present state.

Assessment of the performance differences between the MC1650 and the MC1651 may be based upon the relative behaviors shown in Figures 4 and 7.