MCM72JG32中文資料摩托羅拉數(shù)據(jù)手冊PDF規(guī)格書

The MCM72JG32 and MCM72JG64 are designed to provide a burstable, high performance, 256K/512K L2 cache for the Pentium microprocessor in conjunction with Intel’s Triton chip set. The modules are configured as 32K x 64 and 64K x 64 bits in a 160 pin card edge memory module. Each module uses four of Motorola’s 5 V 32K x 18 or 64K x 18 BurstRAMs and one Motorola 5 V 32K x 8 FSRAM for the tag RAM.

? Pentium–Style Burst Counter on Chip

? Pipelined Data Out

? 160 Pin Card Edge Module

? Address Pipeline Supported by ADSP Disabled with Ex

? All Cache Data and Tag I/Os are TTL Compatible

? Three State Outputs

? Byte Write Capability

? Fast Module Clock Rates: 66 MHz

? Fast SRAM Access Times:15 ns for Tag RAM 9 ns for Data RAMs

? Decoupling Capacitors for Each Fast Static RAM

? High Quality Multi–Layer FR4 PWB with Separate Power and Ground Planes

? I/Os are 3.3 V Compatible on Data RAMs

? Burndy Connector, Part Number: CELP2X80SC3Z48

? Series 20 ? Resistors for Noise Immunity