首頁(yè)>MDU3C-30B2>規(guī)格書(shū)詳情
MDU3C-30B2中文資料DATADELAY數(shù)據(jù)手冊(cè)PDF規(guī)格書(shū)
廠商型號(hào) |
MDU3C-30B2 |
功能描述 | TRIPLE, HCMOS-INTERFACED FIXED DELAY LINE (SERIES MDU3C) |
文件大小 |
47.79 Kbytes |
頁(yè)面數(shù)量 |
4 頁(yè) |
生產(chǎn)廠商 | Data Delay Devices, Inc. |
企業(yè)簡(jiǎn)稱(chēng) |
DATADELAY |
中文名稱(chēng) | Data Delay Devices, Inc.官網(wǎng) |
原廠標(biāo)識(shí) | |
數(shù)據(jù)手冊(cè) | |
更新時(shí)間 | 2025-1-11 13:56:00 |
MDU3C-30B2規(guī)格書(shū)詳情
FUNCTIONAL DESCRIPTION
The MDU3C-series device is a 3-in-1 digitally buffered delay line. The signal inputs (I1-I3) are reproduced at the outputs (O1-O3), shifted in time by an amount determined by the device dash number (See Table). The delay lines function completely independently of each other.
FEATURES
● Three independent delay lines
● Fits standard 14-pin DIP socket
● Low profile
● Auto-insertable
● Input & outputs fully CMOS interfaced & buffered
● 10 T2L fan-out capability
產(chǎn)品屬性
- 型號(hào):
MDU3C-30B2
- 制造商:
DATADELAY
- 制造商全稱(chēng):
Data Delay Devices, Inc.
- 功能描述:
TRIPLE, HCMOS-INTERFACED FIXED DELAY LINE(SERIES MDU3C)
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---|---|---|---|---|---|---|---|
MAGNACHIP |
DFN8 |
68900 |
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詢(xún)價(jià) | |||
MAGNACHIP/美格納 |
DFN5X6 |
90000 |
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詢(xún)價(jià) | |||
MAGNACHIP |
2023+ |
QFN |
80000 |
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詢(xún)價(jià) | ||
MAGNACHIP/美格納 |
2402+ |
QFN |
8324 |
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詢(xún)價(jià) | ||
MAGNACHIP/美格納 |
23+ |
NA/ |
29419 |
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詢(xún)價(jià) | ||
DL |
22+ |
NA |
30000 |
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詢(xún)價(jià) | ||
美格納MAGNACHIPSEMICONDUCTOR |
23+ |
QFN5X6 |
3000 |
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詢(xún)價(jià) | ||
MAGNACHIP/美格納 |
22+ |
DFN-85x6 |
20000 |
深圳原裝現(xiàn)貨正品有單價(jià)格可談 |
詢(xún)價(jià) | ||
MAGNACHIP/美格納 |
23+ |
DFN8 |
50000 |
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詢(xún)價(jià) | ||
MAGNACHIP |
2021+ |
QFN |
100500 |
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詢(xún)價(jià) |