MM74HCT138SJ集成電路（IC）的信號開關(guān)多路復(fù)用器解碼器規(guī)格書PDF中文資料

General Description

The MM74HCT138 decoder utilizes advanced silicon-gate CMOS technology, and are well suited to memory address decoding or data routing applications. Both circuits feature high noise immunity and low power consumption usually associated with CMOS circuitry, yet have speeds comparable to low power Schottky TTL logic.

The MM74HCT138 have 3 binary select inputs (A, B, and C). If the device is enabled these inputs determine which one of the eight normally HIGH outputs will go LOW. Two active LOW and one active HIGH enables (G1, G2A and G2B) are provided to ease the cascading decoders.

The decoders’ output can drive 10 low power Schottky TTL equivalent loads and are functionally and pin equivalent to the 74LS138. All inputs are protected from damage due to static discharge by diodes to VCC and ground.

Features

■ TTL input compatible

■ Typical propagation delay: 20 ns

■ Low quiescent current: 80 μA maximum (74HCT Series)

■ Low input current: 1 μA maximum

■ Fanout of 10 LS-TTL loads