MT48LC128M4A2

SYNCHRONOUS DRAM

GeneralDescription The512MbSDRAMisahigh-speedCMOS,dynamicrandom-accessmemorycontaining536,870,912bits.Itisinternallyconfiguredasaquad-bankDRAMwithasynchronousinterface(allsignalsareregisteredonthepositiveedgeoftheclocksignal,CLK).Eachofthex4’s134,217,728

MT48LC128M4A2

SYNCHRONOUS DRAM

GENERAL DESCRIPTION\nThe 512Mb SDRAM is a high-speed CMOS, dynamic random-access memory containing 536,870,912 bits. It is internally configured as a quad-bank DRAM with a synchronous interface (all signals are registered on the positive edge of the clock signal, CLK). Each of the x4’s 134,217,728-b; ? PC100- and PC133-compliant\n? Fully synchronous; all signals registered on positive\n?? edge of system clock\n? Internal pipelined operation; column address can be\n?? changed every clock cycle\n? Internal banks for hiding row access/precharge\n? Programmable burst lengths: 1, 2, 4, 8, or full pag;

MT48LC128M4A2

512Mb x4, x8, x16 SDRAM

MT48LC128M4A2TG

SYNCHRONOUS DRAM

GeneralDescription The512MbSDRAMisahigh-speedCMOS,dynamicrandom-accessmemorycontaining536,870,912bits.Itisinternallyconfiguredasaquad-bankDRAMwithasynchronousinterface(allsignalsareregisteredonthepositiveedgeoftheclocksignal,CLK).Eachofthex4’s134,217,728

MT48LC128M4A2_07

512Mb x4, x8, x16 SDRAM

MT48LC128M4A2P-75:C TR

Package：54-TSOP（0.400"，10.16mm 寬）；包裝：卷帶（TR） 類別：集成電路（IC） 存儲器 描述：IC DRAM 512MBIT PAR 54TSOP II

MT48LC128M4A2TG-75:C TR

Package：54-TSOP（0.400"，10.16mm 寬）；包裝：卷帶（TR）剪切帶（CT） 類別：集成電路（IC） 存儲器 描述：IC DRAM 512MBIT PAR 54TSOP II

MT48LC128M4A2TG-7E:C

Package：54-TSOP（0.400"，10.16mm 寬）；包裝：托盤 類別：集成電路（IC） 存儲器 描述：IC DRAM 512MBIT PAR 54TSOP II