NT5DS4M32EG中文資料NANOAMP數(shù)據(jù)手冊(cè)PDF規(guī)格書(shū)

General Overview

The NT5DS4M32EG is 134,217,728 bits of double data rate synchronous dynamic RAM organized as 4 x 1,048,576 bits by 32 I/Os. Synchronous features with Data Strobe allow extremely high performance up to 400Mbps/pin. I/O transactions are possible on both edges of the clock. Range of operating frequencies, programmable burst length and programmable latencies allow the device to be useful for a variety of high performance memory system applications.

Features

? VDD = 2.5V±5 , VDDQ = 2.5V±5

? SSTL_2 compatible inputs/outputs

? 4 banks operation

? MRS cycle with address key programs

-CAS latency 2,3 (clock)

-Burst length (2, 4, 8 and Full page)

-Burst type (sequential & interleave)

? Full page burst length for sequential burst type only

? Start address of the full page burst should be even

? All inputs except data & DM are sampled at the rising edge of the system clock

? Differential clock input(CK & /CK)

? Data I/O transaction on both edges of Data strobe

? 4 DQS (1 DQS/Byte)

? DLL aligns DQ and DQS transaction with Clock transaction

? Edge aligned data & data strobe output

? Center aligned data & data strobe input

? DM for write masking only

? Auto & self refresh

? 32ms refresh period (4K cycle)

? 144-Ball FBGA package

? Maximum clock frequency up to 200MHz

? Maximum data rate up to 400Mbps/pin