P89LPC970FDH中文資料恩智浦數據手冊PDF規(guī)格書

General description

The P89LPC970/971/972 is a single-chip microcontroller, available in low cost packages, based on a high performance processor architecture that executes instructions in two to four clocks, six times the rate of standard 80C51 devices. Many system-level functions have been incorporated into the P89LPC970/971/972 in order to reduce component count, board space, and system cost.

Features and benefits

Principal features

■ 2 kB/4 kB/8 kB byte-erasable flash code memory organized into 1 kB sectors and 64-byte pages. Single-byte erasing allows any byte(s) to be used as non-volatile data storage.

■ 256-byte RAM data memory.

■ Two analog comparators with selectable inputs and reference source.

■ Five 16-bit counter/timers (each may be configured to toggle a port output upon timer overflow or to become a PWM output).

■ A 23-bit system timer that can also be used as real-time clock consisting of a 7-bit prescaler and a programmable and readable 16-bit timer.

■ Enhanced UART with a fractional baud rate generator, break detect, framing error detection, and automatic address detection; 400 kHz byte-wide I2C-bus communication port.

■ SPI communication port (pin remap).

■ High-accuracy internal RC oscillator option 7.373 MHz calibrated to ±1 , with clock doubler option, allows operation without external oscillator components. The RC oscillator option is selectable and fine tunable.

■ Watchdog timer with separate on-chip oscillator, nominal 400 kHz/25 kHz, calibrated to ±10 at 400 kHz, requiring no external components. The watchdog prescaler is selectable from eight values.

■ Pin remap for UART, I2C-bus and SPI.

■ 2.4 V to 5.5 V VDD operating range.

■ Enhanced low voltage (brownout) detect allows a graceful system shutdown when power fails.

■ 20-pin TSSOP and DIP packages with 15 I/O pins minimum and up to 18 I/O pins while using on-chip oscillator and reset options.

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