P8XC557E8中文資料恩智浦?jǐn)?shù)據(jù)手冊PDF規(guī)格書

1 FEATURES

· 80C51 Central Processing Unit (CPU)

· 64 kbytes ROM (only P83C557E8)

· 64 kbytes EPROM (only P87C557E8)

· ROM/EPROM Code protection

· 2048 bytes RAM, expandable externally to 64 kbytes

· Two standard 16-bit timers/counters

· An additional 16-bit timer/counter coupled to four

capture registers and three compare registers

· A 10-bit Analog-to-Digital Converter (ADC) with eight

multiplexed analog inputs and programmable autoscan

· Two 8-bit resolution, Pulse Width Modulation outputs

· Five 8-bit I/O ports plus one 8-bit input port shared with

analog inputs

· I2C-bus serial I/O port with byte oriented master and

slave functions

· Full-duplex UART compatible with the standard 80C51

· On-chip Watchdog Timer

· 15 interrupt sources with 2 priority levels (2 to 6 external

sources possible)

· Phase-Locked Loop (PLL) oscillator with 32 kHz

reference and software-selectable system clock

frequency

· Seconds timer

· Software enable/disable of ALE output pulse

· Electromagnetic compatibility improvements

· Wake-up from Power-down by external or seconds

interrupt

· Frequency range for 80C51-family standard oscillator:

3.5 to 16 MHz

· Extended temperature range: -40 to +85 C

· Supply voltage: 4.5 to 5.5 V.

2 GENERAL DESCRIPTION

The 8-bit microcontrollers P80C557E8, P83C557E8 and

P87C557E8 - hereafter referred to as P8xC557E8 - are

manufactured in an advanced CMOS process and are

derivatives of the 80C51 microcontroller family.

The P8xC557E8 contains a volatile 2048 bytes read/write

Data Memory, five 8-bit I/O ports, one 8-bit input port, two

16-bit timer/event counters (identical to the timers of the

80C51), an additional 16-bit timer coupled to capture and

compare latches, a 15-source, two-priority-level,

nested interrupt structure, an 8-input ADC, a dual

Digital-to-Analog Convertor (DAC), Pulse Width

Modulated interface, two serial interfaces (UART and

I2C-bus), a Watchdog Timer, an on-chip oscillator and

timing circuits.

The P8xC557E8 is available in 3 versions:

· P80C557E8: ROMless version

· P83C557E8: containing a non-volatile 64 kbytes mask

programmable ROM

· P87C557E8: containing 64 kbytes programmable

EPROM/OTP.

The P8xC557E8 is a control-oriented CPU with on-chip

Program and Data Memory; it cannot be extended with

external Program Memory. It can access up to 64 kbytes

of external Data Memory. For systems requiring extra

capability, the P8xC557E8 can be expanded using

standard TTL compatible memories and peripherals.

In addition, the P8xC557E8 has two software selectable

reduced power modes: Idle mode and Power-down mode.

The Idle mode freezes the CPU while allowing the RAM,

timers, serial ports, and interrupt system to continue

functioning. The Power-down mode saves the RAM

contents but freezes the oscillator, causing all other chip

functions to be inoperative.The Power-down mode can be

terminated by an external reset, by the seconds interrupt

and by any one of the two external interrupts;

see Section 15.3.

The device also functions as an arithmetic processor

having facilities for both binary and BCD arithmetic as well

as bit-handling capabilities. The instruction set of the

P8xC557E8 is the same as the 80C51 and consists of over

100 instructions: 49 one-byte, 45 two-byte, and

17 three-byte. With a 16 MHz system clock, 58 of the

instructions are executed in 0.75 ms and 40 in 1.5 ms.

Multiply and divide instructions require 3 ms.