PCA9509P集成電路（IC）的信號緩沖器、中繼器、分離器規(guī)格書PDF中文資料

General description

The PCA9509P is a level translating I2C-bus/SMBus repeater with two voltage supplies that enables processor low voltage 2-wire serial bus to interface with standard I2C-bus or SMBus I/O. While retaining all the operating modes and features of the I2C-bus system during the level shifts, it also permits extension of the I2C-bus by providing bidirectional buffering for both the data (SDA) and the clock (SCL) lines, thus enabling the I2C-bus or SMBus maximum capacitance of 400 pF on the higher voltage side. Port A allows a voltage range from 0.8 V to 2.0 V and is overvoltage tolerant. Port B allows a voltage range from 2.3 V to 5.5 V and is overvoltage tolerant. Both port A and port B SDA and SCL pins are high-impedance when the PCA9509P is unpowered.

Features and benefits

■ Bidirectional buffer isolates capacitance and allows 400 pF on port B of the device

■ Voltage level translation from port A (0.8 V to 2.0 V) to port B (2.3 V to 5.5 V)

■ No internal current source on A port to reduce current consumption for portable applications

■ Active HIGH enable input disables current mirrors to reduce standby power

■ Open-drain inputs/outputs

■ Lock-up free operation

■ Supports arbitration and clock stretching across the repeater

■ Accommodates Standard-mode and Fast-mode I2C-bus devices and multiple masters

■ Powered-off high-impedance I2C-bus pins

■ Operating supply voltage range of 0.8 V to 2.0 V on port A, 2.3 V to 5.5 V on port B

■ All pins are 5 V tolerant with respect to ground pin

■ 0 Hz to 400 kHz clock frequency

Remark: The maximum system operating frequency may be less than 400 kHz because of the delays added by the repeater.

■ ESD protection exceeds 2000 V HBM per JESD22-A114 and 1000 V CDM per JESD22-C101

■ Latch-up testing is done to JEDEC Standard JESD78 which exceeds 100 mA

■ Packages offered: TSSOP8, XQFN8