PCA9510

Hot swappable I2C and SMBus bus buffer

DESCRIPTION ThePCA9510andPCA9511arehotswappableI2CandSMBusbuffersthatallowsI/Ocardinsertionintoalivebackplanewithoutcorruptingthedataandclockbuses.Controlcircuitrypreventsthebackplanefrombeingconnectedtothecarduntilastopcommandorbusidleoccursontheba

PHI

PCA9510AD

Hot swappable I2C-bus and SMBus bus buffer; Bidirectional buffer for SDA and SCL lines increases fan-out and prevents SDA and SCL corruption during live board insertion and removal from multipoint backplane systems\nCompatible with Standard-mode I2C-bus, Fast-mode I2C-bus, and SMBus standards\nActive HIGH ENABLE input\nActive HIGH READY open-drain output\nHigh-impedance SDAn and SCLn pins for VCC = 0 V\n1 V precharge on SDAIN and SCLIN inputs\nSupports clock stretching and multiple master arbitration and synchronization\nOperating power supply voltage range: 2.7 V to 5.5 V\n5 V tolerant I/Os\n0 Hz to 400 kHz clock frequency\nESD protection exceeds 2000 V HBM per JESD22-A114, 200 V MM per JESD22-A115, and 1000 V CDM per JESD22-C101\nLatch-up testing is done to JEDEC Standard JESD78 which exceeds 100 mA\nPackages offered: SO8, TSSOP8 (MSOP8)\n;

The PCA9510A is a hot swappable I2C-bus and SMBus buffer that allows I/O card insertion into a live backplane without corrupting the data and clock buses. Control circuitry prevents the backplane from being connected to the card until a stop command or bus idle occurs on the backplane without bus contention on the card. When the connection is made, the PCA9510A provides bidirectional buffering, keeping the backplane and card capacitances isolated.\nThe PCA9510A has no rise time accelerator circuitry to prevent interference when there are multiple devices in the same system. The PCA9510A incorporates a digital ENABLE input pin, which enables the device when asserted HIGH and forces the device into a Low current mode when asserted LOW, and an open-drain READY output pin, which indicates that the backplane and card sides are connected together (HIGH) or not (LOW).\nDuring insertion, the PCA9510A SDAIN and SCLIN pins (inputs only) are precharged to 1 V to minimize the current required to charge the parasitic capacitance of the chip.\nRemark: The dynamic offset design of the PCA9510A/11A/12A/13A/14A I/O drivers allow them to be connected to another PCA9510A/11A/12A/13A/14A device in series or in parallel and to the A side of the PCA9517. The PCA9510A/11A/12A/13A/14A cannotconnect to the static offset I/Os used on the PCA9515/15A/16/16A/18 or PCA9517 B side or P82B96 Sx/y side.\n

恩XP

PCA9510ADP

Hot swappable I2C-bus and SMBus bus buffer; Bidirectional buffer for SDA and SCL lines increases fan-out and prevents SDA and SCL corruption during live board insertion and removal from multipoint backplane systems\nCompatible with Standard-mode I2C-bus, Fast-mode I2C-bus, and SMBus standards\nActive HIGH ENABLE input\nActive HIGH READY open-drain output\nHigh-impedance SDAn and SCLn pins for VCC = 0 V\n1 V precharge on SDAIN and SCLIN inputs\nSupports clock stretching and multiple master arbitration and synchronization\nOperating power supply voltage range: 2.7 V to 5.5 V\n5 V tolerant I/Os\n0 Hz to 400 kHz clock frequency\nESD protection exceeds 2000 V HBM per JESD22-A114, 200 V MM per JESD22-A115, and 1000 V CDM per JESD22-C101\nLatch-up testing is done to JEDEC Standard JESD78 which exceeds 100 mA\nPackages offered: SO8, TSSOP8 (MSOP8)\n;

The PCA9510A is a hot swappable I2C-bus and SMBus buffer that allows I/O card insertion into a live backplane without corrupting the data and clock buses. Control circuitry prevents the backplane from being connected to the card until a stop command or bus idle occurs on the backplane without bus contention on the card. When the connection is made, the PCA9510A provides bidirectional buffering, keeping the backplane and card capacitances isolated.\nThe PCA9510A has no rise time accelerator circuitry to prevent interference when there are multiple devices in the same system. The PCA9510A incorporates a digital ENABLE input pin, which enables the device when asserted HIGH and forces the device into a Low current mode when asserted LOW, and an open-drain READY output pin, which indicates that the backplane and card sides are connected together (HIGH) or not (LOW).\nDuring insertion, the PCA9510A SDAIN and SCLIN pins (inputs only) are precharged to 1 V to minimize the current required to charge the parasitic capacitance of the chip.\nRemark: The dynamic offset design of the PCA9510A/11A/12A/13A/14A I/O drivers allow them to be connected to another PCA9510A/11A/12A/13A/14A device in series or in parallel and to the A side of the PCA9517. The PCA9510A/11A/12A/13A/14A cannotconnect to the static offset I/Os used on the PCA9515/15A/16/16A/18 or PCA9517 B side or P82B96 Sx/y side.\n

恩XP

PCA9510D

Hot swappable I²C-bus and SMBus bus buffer; ?Bidirectional buffer for SDA and SCL lines increases fanout and prevents SDA and SCL corruption during live board insertion and removal from multi-point backplane systems\n?Compatible with I2C-bus Standard-mode, I2C-bus Fast-mode, and SMBus standards\n?Active HIGH ENABLE input\n?Active HIGH READY open-drain output\n?High-impedance SDA and SCL pins for VCC = 0 V\n?1 V precharge on all SDA and SCL lines (IN only)\n?Supports clock stretching and multiple master arbitration/synchronization\n?Operating power supply voltage range: 2.7 V to 5.5 V\n?5.5 V tolerant I/Os\n?0 Hz to 400 kHz clock frequency\n?ESD protection exceeds 2000 V HBM per JESD22-A114, 200 V MM per JESD22-A115, and 1000 V CDM per JESD22-C101\n?Latch-up testing is done to JEDEC Standard JESD78 which exceeds 100 mA\n?Packages offered: SO8, TSSOP8 (MSOP8)\n;

Overview The PCA9510 is a hot swappable I2C-bus and SMBus buffer that allows I/O card insertion into a live backplane without corrupting the data and clock buses. Control circuitry prevents the backplane from being connected to the card until a STOP command or bus idle occurs on the backplane without bus contention on the card. When the connection is made, the PCA9510 provides bidirectional buffering, keeping the backplane and card capacitances isolated.\n

恩XP

PCA9510D

Hot swappable I2C and SMBus bus buffer

DESCRIPTION ThePCA9510andPCA9511arehotswappableI2CandSMBusbuffersthatallowsI/Ocardinsertionintoalivebackplanewithoutcorruptingthedataandclockbuses.Controlcircuitrypreventsthebackplanefrombeingconnectedtothecarduntilastopcommandorbusidleoccursontheba

PHI

PCA9510DP

Hot swappable I2C and SMBus bus buffer

DESCRIPTION ThePCA9510andPCA9511arehotswappableI2CandSMBusbuffersthatallowsI/Ocardinsertionintoalivebackplanewithoutcorruptingthedataandclockbuses.Controlcircuitrypreventsthebackplanefrombeingconnectedtothecarduntilastopcommandorbusidleoccursontheba

PHI

PCA9510A

Hot swappable I2C-bus and SMBus bus buffer

PHI

PCA9510A

Hot swappable I2C-bus and SMBus bus buffer

ETC

PCA9510A

Smart, simple solutions for the 12 most common design concerns

ETC

PCA9510AD

Hot swappable I2C-bus and SMBus bus buffer

PHI