PCA9549PW

Octal bus switch with individually I2C-bus controlled enables

Generaldescription ThePCA9549provideseightbitsofhighspeedTTL-compatiblebusswitchingcontrolledbytheI2C-bus.ThelowON-stateresistanceoftheswitchallowsconnectionstobemadewithminimalpropagationdelay.AnyindividualAtoBchannelorcombinationofchannelscanbeselec

PCA9549PW

Octal bus switch with individually I2C-bus controlled enables; \n\n?8-bit bus switch (CBT)\n\n?5 Ω switch connection between two ports\n\n?I2C-bus interface logic; compatible with SMBus standards\n\n?Active LOW RESET input\n\n?3 address pins allowing up to 8 devices on the I2C-bus\n\n?Bit selection via I2C-bus, in any combination\n\n?Power-up with all bits deselected\n\n?Low Ron switches\n\n?No glitch on power-up\n\n?Supports hot insertion\n\n?Low standby current\n\n?Operating power supply voltage range of 2.3 V to 5.5 V\n\n?5 V tolerant inputs\n\n?0 Hz to 400 kHz clock frequency\n\n?ESD protection exceeds 2000 V HBM per JESD22-A114, 200 V MM per JESD22-A115 and 1000 V CDM per JESD22-C101\n\n?Latch-up testing is done to JEDEC Standard JESD78 which exceeds 100 mA\n\n?Packages offered: SO24, TSSOP24, HVQFN24\n\n\n;

OverviewThe PCA9549 provides eight bits of high speed TTL-compatible bus switching controlled by the I2C-bus. The low ON-state resistance of the switch allows connections to be made with minimal propagation delay. Any individual A to B channel or combination of channels can be selected via the I2C-bus, determined by the contents of the programmable Control register. When the I2C-bus bit is HIGH (logic 1), the switch is on and data can flow from Port A to Port B, or vice versa. When the I2C-bus bit is LOW (logic 0), the switch is open, creating a high-impedance state between the two ports, which stops the data flow.\n An active LOW reset input (RESET) allows the PCA9549 to recover from a situation where the I2C-bus is stuck in a LOW state. Pulling the RESET pin LOW resets the I2C-bus state machine and causes all the bits to be open, as does the internal power-on reset function.\n Three address pins allow up to eight devices on the same bus.\n

9549

MACHINESCREWPANPHILLIPS10-32

9549

36wayCentronicsCables

AD9549

DualInputNetworkClockGenerator/Synchronizer

GENERALDESCRIPTION TheAD9549providessynchronizationformanysystems,includingsynchronousopticalnetworks(SONET/SDH).TheAD9549generatesanoutputclock,synchronizedtooneoftwoexternalinputreferences.Theexternalreferencesmaycontainsignificanttimejitter,alsospecifiedas

AD9549

DualInputNetworkClockGenerator/Synchronizer

GENERALDESCRIPTION TheAD9549providessynchronizationformanysystems,includingsynchronousopticalnetworks(SONET/SDH).TheAD9549generatesanoutputclock,synchronizedtooneoftwoexternalinputreferences.Theexternalreferencesmaycontainsignificanttimejitter,alsospecifiedas

AD9549ABCPZ

DualInputNetworkClockGenerator/Synchronizer

GENERALDESCRIPTION TheAD9549providessynchronizationformanysystems,includingsynchronousopticalnetworks(SONET/SDH).TheAD9549generatesanoutputclock,synchronizedtooneoftwoexternalinputreferences.Theexternalreferencesmaycontainsignificanttimejitter,alsospecifiedas

AD9549APCBZ

DualInputNetworkClockGenerator/Synchronizer

GENERALDESCRIPTION TheAD9549providessynchronizationformanysystems,includingsynchronousopticalnetworks(SONET/SDH).TheAD9549generatesanoutputclock,synchronizedtooneoftwoexternalinputreferences.Theexternalreferencesmaycontainsignificanttimejitter,alsospecifiedas

AD9549BCPZ

DualInputNetworkClockGenerator/Synchronizer

GENERALDESCRIPTION TheAD9549providessynchronizationformanysystems,includingsynchronousopticalnetworks(SONET/SDH).TheAD9549generatesanoutputclock,synchronizedtooneoftwoexternalinputreferences.Theexternalreferencesmaycontainsignificanttimejitter,alsospecifiedas

AD9549XCPZ

DualInputNetworkClockGenerator/Synchronizer

GENERALDESCRIPTION TheAD9549providessynchronizationformanysystems,includingsynchronousopticalnetworks(SONET/SDH).TheAD9549generatesanoutputclock,synchronizedtooneoftwoexternalinputreferences.Theexternalreferencesmaycontainsignificanttimejitter,alsospecifiedas