R7FA6T2BD3CNB中文資料瑞薩數(shù)據(jù)手冊(cè)PDF規(guī)格書(shū)

■ Arm? Cortex?-M33 Core

● Armv8-M architecture with the main extension

● Maximum operating frequency: 240 MHz

● Arm Memory Protection Unit (Arm MPU)

– Protected Memory System Architecture (PMSAv8)

– Secure MPU (MPU_S): 8 regions

– Non-secure MPU (MPU_NS): 8 regions

● SysTick timer

– Embeds two SysTick timers: Secure and Non-secure instance

– Driven by LOCO or system clock

● CoreSight? ETM-M33

■ Memory

● Up to 512-KB code flash memory

● 16-KB data flash memory (125,000 program/erase (P/E) cycles)

● 64-KB SRAM

■ Connectivity

● Serial Communications Interface (SCI) × 6

– Asynchronous interfaces

– 8-bit clock synchronous interface

– Smart card interface

– Simple IIC

– Simple SPI

– Simple LIN

– Manchester coding

● I2C bus interface (IIC) × 2

– Transfer at up to 3.2 Mpbs (high speed mode)

● Serial Peripheral Interface (SPI) × 2

● CAN with Flexible Data-rate (CANFD)

■ Analog

● 12-bit A/D Converter (ADC) × 2

– Sample-and-hold circuits × 6

– Programmable Gain Amplifier × 4

● High-Speed Analog Comparator (ACMPHS) × 4

● 12-bit D/A Converter (DAC12) × 4

● Temperature Sensor (TSN)

■ Timers

● General PWM Timer 32-bit (GPT32) with High Resolution × 4

– 156 ps resolution in 200 MHz

● General PWM Timer 32-bit (GPT32) × 6

● Low Power Asynchronous General Purpose Timer (AGT) × 2

■ Security and Encryption

● Secure Cryptographic Engine (SCE5)

– Symmetric algorithms: AES

– Hash-value generation: GHASH

– 128-bit unique ID

● Arm? TrustZone?

– Up to three regions for the code flash

– Up to two regions for the data flash

– Up to three regions for the SRAM

– Individual secure or non-secure security attribution for each

peripheral

● Device lifecyle management