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SI5324C-C-GM集成電路(IC)的應用特定時鐘/定時規(guī)格書PDF中文資料

廠商型號 |
SI5324C-C-GM |
參數屬性 | SI5324C-C-GM 封裝/外殼為36-VFQFN 裸露焊盤;包裝為管件;類別為集成電路(IC)的應用特定時鐘/定時;產品描述:IC CLOCK MULT 2KHZ-346MHZ 36VQFN |
功能描述 | ANY-FREQUENCY PRECISION CLOCK MULTIPLIER/ JITTER ATTENUATOR |
封裝外殼 | 36-VFQFN 裸露焊盤 |
文件大小 |
518.88 Kbytes |
頁面數量 |
72 頁 |
生產廠商 | Silicon Laboratories |
企業(yè)簡稱 |
SILABS |
中文名稱 | Silicon Laboratories官網 |
原廠標識 | ![]() |
數據手冊 | |
更新時間 | 2025-6-21 23:00:00 |
人工找貨 | SI5324C-C-GM價格和庫存,歡迎聯(lián)系客服免費人工找貨 |
SI5324C-C-GM規(guī)格書詳情
Description
The Si5324 is a low-bandwidth, jitter-attenuating, precision clock multiplier for applications requiring sub 1 ps jitter performance with loop bandwidths between 4 Hz and 525 Hz. The Si5324 accepts two input clocks ranging from 2 kHz to 710 MHz and generates two output clocks ranging from 2 kHz to 945 MHz and select frequencies to 1.4 GHz. The two outputs are divided down separately from a common source. The Si5324 can also use its external reference as a clock source for frequency synthesis. The device provides virtually any frequency translation combination across this operating range. The Si5324 input clock frequency and clock multiplication ratio are programmable via an I2C or SPI interface. The Si5324 is based on Silicon Laboratories 3rd-generation DSPLL? technology, which provides any-frequency synthesis and jitter attenuation in a highly integrated PLL solution that eliminates the need for external VCXO and filter components. The DSPLL loop bandwidth is digitally programmable, providing jitter performance optimization at the application level. The Si5324 is ideal for providing clock multiplication and jitter attenuation in high performance timing applications.
Features
■ Generates any frequency from
2 kHz to 945 MHz and select
frequencies to 1.4 GHz from an
input frequency of 2 kHz to 710 MHz
■ Ultra-low jitter clock outputs as low
as 290 fs rms (12 kHz–20 MHz), 320 fs rms (50 kHz–80 MHz)
■ Integrated loop filter with
selectable loop bandwidth (4– 525 Hz)
■ Meets ITU-T G.8251 and Telcordia
GR-253-CORE jitter specification
■ Hitless input clock switching with phase build-out
■ Freerun, Digital Hold operation
■ Configurable signal format per
output (LVPECL, LVDS, CML, CMOS)
■ Support for ITU G.709 and custom
FEC ratios (255/238, 255/237,
255/236, 239/237, 66/64, 239/238, 15/14, 253/221, 255/238)
■ LOL, LOS, FOS alarm outputs
■ I2C or SPI programmable
■ On-chip voltage regulator with high PSNR
■ Single supply 1.8 ±5, 2.5 ±10, or 3.3 V ±10
■ Small size: 6 x 6 mm 36-lead QFN
■ Pb-free, ROHS-compliant
Applications
■ Broadcast video –3G/HD/SD-SDI, Genlock
■ Packet Optical Transport Systems (P-OTS), MSPP
■ OTN/OTU-1/2/3/4 Asynchronous
Demapping (Gapped Clock)
■ SONET OC-48/192/768, SDH/STM-16/64/256 line cards
■ 1/2/4/8/10G Fibre Channel line cards
■ GbE/10/40/100G Synchronous Ethernet (LAN/WAN)
■ Data converter clocking
■ Wireless base stations
■ Test and measurement
產品屬性
- 產品編號:
SI5324C-C-GM
- 制造商:
Skyworks Solutions Inc.
- 類別:
集成電路(IC) > 應用特定時鐘/定時
- 系列:
DSPLL?
- 包裝:
管件
- PLL:
是
- 主要用途:
以太網(WAN),SONET/SDH/STM,視頻
- 輸入:
時鐘
- 輸出:
CML,CMOS,LVDS,LVPECL
- 比率 - 輸入:
2:2
- 差分 - 輸入:
是/是
- 頻率 - 最大值:
346MHz
- 電壓 - 供電:
1.71V ~ 3.63V
- 工作溫度:
-40°C ~ 85°C
- 安裝類型:
表面貼裝型
- 封裝/外殼:
36-VFQFN 裸露焊盤
- 供應商器件封裝:
36-QFN(6x6)
- 描述:
IC CLOCK MULT 2KHZ-346MHZ 36VQFN
供應商 | 型號 | 品牌 | 批號 | 封裝 | 庫存 | 備注 | 價格 |
---|---|---|---|---|---|---|---|
SILICON芯科 |
24+ |
N/A |
7998 |
原廠可訂貨,技術支持,直接渠道??珊灡9┖贤?/div> |
詢價 | ||
SILICON |
24+ |
NA |
6000 |
全新原裝正品現貨,假一賠佰 |
詢價 | ||
SILICON LABS/芯科 |
22+ |
QFN |
100000 |
代理渠道/只做原裝/可含稅 |
詢價 | ||
SILICON/芯科 |
25+ |
QFN |
54658 |
百分百原裝現貨 實單必成 |
詢價 | ||
Skyworks Solutions I |
21+ |
QFN36 |
50 |
一級代理,專注軍工、汽車、醫(yī)療、工業(yè)、新能源、電力 |
詢價 | ||
SILICON LABS/芯科 |
22+ |
QFN |
30000 |
進口原裝現貨供應,原裝 假一罰十 |
詢價 | ||
NA |
23+ |
NA |
26094 |
10年以上分銷經驗原裝進口正品,做服務型企業(yè) |
詢價 | ||
Silicon Labs |
23+ |
QFN |
22000 |
一級代理原裝正品,實單必成。 |
詢價 | ||
SILICON LABS(芯科) |
24+ |
QFN-36 |
13048 |
原廠可訂貨,技術支持,直接渠道??珊灡9┖贤?/div> |
詢價 | ||
SILICON LABS(芯科) |
24+ |
QFN-36 |
10000 |
現貨庫存,原裝正品??珊?/div> |
詢價 |